Stress-induced Charge Trapping Research Articles

(Invited) ALD HfO2/β-Ga2O3 Reliability for Future Power Devices

The ultra-wide bandgap (UWBG) semiconductor, β-gallium oxide, has shown great potential in power devices due to its excellent electrical properties and availability of high-quality single-crystalline substrates. Significant progress has been made in the development of β-Ga2O3 metal-oxide-semiconductor (MOS) devices, but further progress will require optimization of the gate-dielectric interface. In this talk, I will describe the investigation of HfO2 dielectric reliability on β-Ga2O3 for future power devices. I fabricated β-Ga2O3 (010) MOS capacitors with atomic layer deposited (ALD) HfO2 and used capacitance-voltage (C-V) and current density-voltage (J-V) techniques to analyze the electrical reliability of ALD HfO2/β-Ga2O3 MOSCAPs. Positive bias stress measurements indicated that HfO2/β-Ga2O3 MOSCAPs are more susceptible to charge trapping at lower electric stress fields compared to HfO2/Si MOSCAPs, likely due to the smaller conduction band offset between HfO2 and β-Ga2O3. Initial flatband voltage shifts were observed for C-V sweeps of HfO2/β-Ga2O3 MOSCAPs, showing the significance of border traps within the dielectric. The lack of mobile holes in the β-Ga2O3 impedes the recombination of these trapped charges in the dielectric while the MOSCAP is in depletion. We observed full recovery from stress-induced charge trapping in the HfO2/β-Ga2O3 MOSCAPs upon deep ultra-violet illumination. The negative valence band offset between the dielectric and semiconductor allows the recombination of photo-generated holes with the trapped dielectric charges [1]. Because many fabrication steps require high temperature processing, we also investigated the thermal reliability of the ALD HfO2/β-Ga2O3 (010) interface. Negligible Ga atom diffusion was observed in secondary ion mass spectrometry (SIMS) depth profiles for anneals at temperatures up to 850°C in N2 environment for 10 minutes. Significant Ga diffusion into the HfO2 layer was observed upon annealing at 900°C, resulting in a severely degraded MOS structure. Additional analysis was performed to investigate the impact of high temperature processing on the MOS electrical characteristics [2].H.N.M was supported by a National Science Foundation Graduate Research Fellowship under Grant No. DGE 1256260. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. Portions of this work were performed at the Lurie Nanofabrication Facility and J. D. Hanawalt X-Ray MicroAnalysis Laboratory, which are supported by the College of Engineering at the University of Michigan.[1] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Charge trapping and recovery in ALD HfO2/β-Ga2O3 (010) MOS capacitors,” Semicond. Sci. Technol., vol. 36, no. 4, p. 04LT01, Mar. 2021, doi:10.1088/1361-6641/abe880.[2] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Effects of High Temperature Annealing on the Atomic Layer Deposited HfO2 /β-Ga2O3 (010) interface,” Journal of Applied Physics, Accepted.

Charge trapping and recovery in ALD HfO2/β-Ga2O3 (010) MOS capacitors

The reliability of atomic layer deposited HfO2 β-Ga2O3 (010) MOS capacitors (MOSCAPs) was tested using constant voltage stress measurements. The HfO2/β-Ga2O3 MOSCAPs showed significant positive flatband voltage shifts (ΔV fb) of up to +1.3 V after 4.3 × 103 s stress, likely due to electron trapping in the dielectric in border traps. Results indicate there may exist an electric field threshold between 0.98 and 1.23 MV cm−1 for electron trapping to occur in these MOSCAPs. Deep ultra-violet (DUV) illumination enables full recovery from the charge trapping. In contrast, HfO2/Si MOSCAPs do not recover under DUV illumination and exhibit smaller voltage shifts upon initial testing. We thus surmise that the type-II band alignment between HfO2 and β-Ga2O3 enables full recovery from stress-induced charge trapping via photogeneration of electron–hole pairs and hole transport across the negative valence band offset. This hypothesis is borne out by the observation of photo-current in the HfO2/β-Ga2O3 MOSCAPs when biased in depletion. In sum, HfO2/β-Ga2O3 MOS structures appear to be susceptible to flatband voltage shifts during stress bias due to the availability and accessibility of border traps. This work highlights the unique challenges in forming reliable ultra-wide band gap MOS devices, due to the significant role that border traps in the lower half of the insulator band gap play in bias stress response.

Stress-induced charge trapping and electrical properties of atomic-layer-deposited HfAlO/Ga2O3 metal–oxide–semiconductor capacitors

Electrical properties and trapping characteristics of an atomic layer deposited Al-rich HfAlO/β-Ga2O3 capacitor were evaluated via constant-voltage stress (CVS), capacitance–voltage (C–V), and current–voltage (I–V) measurements. The magnitude of the stress-induced charge trapping increases with increasing voltage and time. The effective charges (Neff) including the ‘border’ traps located in near-interface oxide, interface traps (Dit) of HfAlO/β-Ga2O3 interface, and fixed charges contribute significantly to the observed charge trapping, and it is found that interface traps contribute more under a large stress bias, compared with ‘border’ traps. In addition, the effective charge density is increased with stress time, implying that the contribution of negative sheet charges during the CVS process might not be negligible. Measurements of oxide permittivity (10.74), interface state density (Dit ~ 1 × 1012 eV−1 cm−2), and gate leakage current (1.18 × 10−5 A cm−2 at +10 V) have been extracted, suggesting the great electrical properties of Al-rich HfAlO/β-Ga2O3 MOSCAP. According to the above analysis, Al-rich HfAlO is an attractive candidate for normally off Ga2O3 transistors.

Physical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses

In this paper, the drain induced barrier lowering (DIBL) variations in High-k/Metal gate n-channel metal–oxide–semiconductor field effect transistor under the normal and reverse channel hot carrier (CHC) stress are studied. It is found that DIBL decreases under normal CHC stress mode while increases under reverse CHC mode. The different DIBL variation under normal and reverse CHC stresses is proposed to be attributed to stress-induced charge trapping by cold carriers from the channel rather than hot carriers from the pinch off region, which can be explained by energy band bending theory.

Effects of constant voltage stress on p- and n-type organic thin film transistors with poly(methyl methacrylate) gate dielectric

We performed constant voltage stress on oligothiophene-based p- and n-type organic thin-film-transistors, in the accumulation regime. The stress induced charge trapping, mobility degradation and defect generation. The specific kinetics depends not only on the applied bias value and polarity, but also on the semiconductor type. Stress on PMMA capacitors (without the semiconductor film) revealed that most of the degradation is largely originated by the interaction with the semiconductor layer, which enhances charge injection.

Constant voltage stress induced charge trapping and detrapping characteristics of the Si3N4 uniaxial strained n-channel metal-oxide-semiconductor field-effect-transistor with fluorinated HfO2/SiON gate stack

Charge trapping and detrapping characteristics of Si3N4 contact etch stop layer (SiN CESL) uniaxial strained n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) with fluorinated HfO2/SiON gate stack have been investigated for the first time. Smaller threshold voltage shift can consequently obtain for the SiN CESL strained nMOSFET with fluorinated HfO2/SiON gate stack, primarily due to passivation of oxygen vacancies and dangling bonds by either nitrogen or fluorine atoms. However, the SiN CESL strained nMOSFET with fluorinated gate stack inevitably exhibits less charge detrapping ratio, which means greater part of stress-induced charges would remain in the gate stack after nitrogen or fluorine incorporation, respectively.

Reliability characterization of stress-induced charge trapping in HfO2 by electrostatic discharge impulse stresses

The charge trapping characteristics of HfO2 dielectric under the electrostatic discharge (ESD) high-field current impulses were studied. It is found that the charge trapping phenomenon is different from that of the conventional dc stress. The results show the interface-trapped charges are built at the low stress regime, but the positive oxide-trapped charges are rapidly built up while increasing the stress voltage, which eventually dominates the oxide breakdown. The origin of the positive oxide-trapped charges at the medium stress regime is most likely the hole trapping. At high stress regime, the main contribution of the positive oxide-trapped charges results from the electric-field enhanced defect generation. Using the Fowler derivative method, the degradation characteristics of HfO2 oxides under the ESD stress are investigated. Compared with SiO2, the severer ESD-induced charge trapping in HfO2 dielectric is observed which can be elucidated by the inherent bonding nature of metal oxide.

Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses

We have investigated the static and dynamic bias stress-induced charge trapping and detrapping phenomenon in amorphous indium–gallium–zinc oxide thin film transistors. It is observed that the charges trapped after electron injection in the interface and bulk traps are unstable and slowly decay over time. The stretched-exponential equation, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is successfully applied in fitting the time dependence of the threshold voltage shift during the stress and recovery phases under dynamic stresses. The characteristic time constants decrease with increasing temperature and drain bias during the recovery phase. Under dynamic stresses with various frequencies, the threshold voltage shift strongly depends on the frequency of dynamic stresses, i.e., a high frequency stress results in a small threshold voltage shift and a long lifetime. The stress-induced threshold shift phenomenon is observed to be relieved after a long-time low temperature post thermal annealing process and device passivation with an aluminum oxide layer.

Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes

Strong polarity dependent charge trapping effects have been observed in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current–voltage (I–V) and capacitance–voltage (C–V) sensing techniques. For substrate injection, electron trapping occurs mainly in the bulk of the Al2O3, resulting in positive voltage shifts for both I–V and C–V measurements. In the case of gate injection, positive charge trapping near the SiO2/Al2O3 interface leads to negative voltage shifts for C–V and positive shifts for I–V measurements. The polarity dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielectric.

Evaluation of MOS devices as mechanical stress sensors

The influence of mechanical stress on metal-oxide-semiconductor (MOS) devices has been studied and analyzed for their applicability as in-situ sensors that are capable of measuring packaging induced and/or externally applied stress. Either compressive or tensile stress would alter the electrical characteristics of MOS devices in a regular pattern and that can be explained by substrate piezoresistivity. The regularity of electrical parameter variation of MOSFETs and the high sensitivity in correspondence with mechanical stress have made them very attractive as stress sensors since they may provide accurate and localized stress-state measurements. Through careful analysis, appropriate MOSFET-based sensors may be designed for proper on-site stress measurement in packaging and other stress detection applications. In addition, the mechanical stress also cause MOS devices to exhibit shorter lifetime that can be attributed to the occurrence of stress-induced charge-trapping sites in gate oxide. For MOSFETs utilized as stress sensors, the reliability issue related to mechanical stress has to be accounted and certain modification of stress-state extraction procedure will be needed to maintain valid stress measurement.