<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Forward body biasing is a promising approach for realizing optimum threshold-voltage <formula formulatype="inline"><tex Notation="TeX">$(V_{\rm TH})$</tex></formula> scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias <formula formulatype="inline"><tex Notation="TeX">$(V_{F})$</tex></formula> decreases the depletion width <formula formulatype="inline"><tex Notation="TeX">$(X_{\rm DEP})$</tex></formula> in the channel region, it reduces <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small <formula formulatype="inline"><tex Notation="TeX">$X_{\rm DEP}$</tex> </formula>) at low <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for <formula formulatype="inline"><tex Notation="TeX">$\vert V_{F}\vert$</tex></formula> should be set at 0.6–0.7 V, which is sufficient to realize significant advantages of forward body biasing. </para>