Statistical Circuit Simulation Research Articles

Generative Modeling of Semiconductor Devices for Statistical Circuit Simulation

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit’s behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device’s physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs.

Accurate Multi-segment Probability Density Estimation Through Moment Matching

The impact of process variations continues to grow as transistor feature size shrinks. Such variations in transistor parameters lead to variations and unpredictability in circuit output and may ultimately cause them to violate specifications leading to circuit failure. In fact, timely failures in critical circuits may lead to catastrophic failures in the entire chip. As such, statistical modeling of circuit behavior is becoming increasingly important. However, existing statistical circuit simulation approaches fail to accurately and efficiently analyze the high sigma behavior of probabilistic circuit output. To this end, we propose PDM (Piecewise Distribution Model) - a piecewise distribution modeling approach via moment matching using maximum entropy to model the high sigma behavior of analog/mixed-signal (AMS) circuit probability distributions. PDM is independent of the number of input dimensions and matches region specific probabilistic moments which allows for significantly greater accuracy compared to other moment matching approaches. PDM also utilizes Spearman’s rank correlation coefficient to select the optimal approximation for the tail of the distribution. Experiments on a known mathematical distribution and various circuits obtain accurate results up to 4.8 sigma with 2-3 orders of speedup relative to Monte Carlo. PDM also demonstrates better accuracy while compared against other state-of-the-art statistical modeling approaches, such as maximum entropy, importance sampling, and subset simulation.

Reliability-Aware Statistical BSIM Compact Model Parameter Generation Methodology

This article presents an accurate, reliability-aware statistical Berkeley short-channel IGFET Model 4 (BSIM4) compact model parameter generation methodology using the generalized lambda distribution (GLD) method. Using this methodology, compact model parameter sets can be generated “on the fly” beyond the limitation of the number of compact models extracted from the TCAD simulation. The generated unlimited parameter sets enable circuit designer for the statistical circuit simulation. An analytical model has been developed to interpolate TCAD simulation data points, which enables statistical compact model parameter sets to be generated at any aging level. The capability to generate such intermediate aging model parameters at trap densities that were not physically simulated has important application in statistical circuit simulation, opening up the possibility to include accurately reliability assessment in circuit design. An aging model that can transfer trap density to stress/aging time is an integral part of the presented methodology. The accuracy of the compact model parameter generation methodology is validated by comparing the new generated compact model parameter sets at an interpolated trap density, against physical “atomistic” 3-D TCAD simulation. The compact model parameter generation methodology enables the accurate investigation of the influence of statistical variability and bias temperature instability (BTI)-induced aging at circuit level.

Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation

Table-based models of semiconductor devices are an attractive solution if a physics-based analytical model of the device cannot be found or has insufficient accuracy. Moreover, table-based models offer easy tradeoff between evaluation speed and accuracy. Traditionally, the biggest disadvantage of this class of model has been the inability to take device variability into account. This paper presents a table-based model that can handle process-induced variations of multiple device parameters. The impact of those variations on device operation is modeled analytically using special transformations of the current–voltage and charge–voltage characteristics of the nominal (i.e., variation-free) device. In contrast to multidimensional interpolation between the ${I}$ – ${V}$ and ${Q}$ – ${V}$ curves of “corner” devices, the proposed approach is much less costly in terms of CPU time, RAM use, and time dedicated to device characterization. The model has been successfully used in statistical simulations of an amplifier and ring oscillator built with VeSFETs—dual-gate junctionless transistors.

Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

An Analytical Yield Model for Zero-<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {GS}}$ </tex-math></inline-formula>-Load Thin-Film Transistor Logic Circuits

This letter presents an analytical circuit yield model for zero-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> -load thin-film transistor (TFT) logic circuits, which describes the circuit yield as a function of the circuit complexity, threshold voltage dispersion of TFTs, and circuit design parameters. By comparing the calculation result through the model with that by Monte Carlo statistical circuit simulations, the model is proved to be capable of providing a simple and effective way to predict the yield of a given zero-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> -load TFT circuit design, and is thus applicable for TFT performance evaluation or device and process optimization.

EFFECT OF PROCESS VARIATIONS ON AN OTFT COMPACT MODEL PARAMETERS

We have studied the effect of some of the possible deviations on the values of the extracted parameters of a specific OTFT model, considering OTFTs designed using P 3 HT as semiconductor layer, PMMA as insulator, bottom gate, and top gold contacts. Specifically, we have studied the influence of misposition or misalignment of the masks, the effect of imperfections of etching, and the effect of variations on the layer deposition process. These effects have been simulated using the Silvaco Athena software, and they have been modeled as horizontal shifts of the etching windows and variations of the layers thickness. Once the devices were defined, they were simulated using Silvaco Atlas, and parameter extraction was performed using a specifically developed algorithm. We have found a strong correlation among some of the physical parameters and the model parameters that may offer useful insight for process optimization. Moreover, strong correlations have been found also among the model parameters. We have used these results to develop a Monte Carlo model, suitable for statistical circuit simulation.

Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction

Abstract This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I–V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.

Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation

In this paper, a new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both the I-V and C-V characteristics of a transistor, finite data points are identified based on their physical meanings and their importance in circuit operation. The impact of process and design variations is embedded into these key points using analytical expressions. During the simulation, the entire I -V and C -V curves are interpolated from these points with simple polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A to support generic circuit simulators. The accuracy and convergence of the proposed model are comprehensively evaluated through a set of benchmark circuits, including nand, a pass-gate, latches, AOI, ring oscillators, and an adder. Compared to SPICE simulations with the BSIM models, the simulation time can be reduced by 7 times in transient analysis and more than 9 times in Monte-Carlo simulations.

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology

A generalized methodology for modeling the effects of process variations on circuit delay performance is proposed by directly relating the variations in process parameters to variations in delay metric of a digital circuit. The 2-input nand gate is used as a library element for 65 nm gate length technology, whose delay is extensively characterized by mixed-mode simulations. This information is then used in a general-purpose circuit simulator SEQUEL, by incorporating appropriate templates for the nand gate library. A 4-bit times 4-bit Wallace tree multiplier circuit, consisting of about 300 2-input nand gates, is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized by an extensive Monte Carlo analysis. To extend this methodology for a generic technology library with a variety of library elements, modeling of nand gate delays by response surface methodology (RSM), in terms of process parameters, is carried out using design of experiments (DOE). A simple piecewise quadratic model, based on the least squares method (LSM), is proposed for one-parameter variation to address significant cubic effects observed in the delay response function. Then, a hybrid model for gate delays is generated by superimposing the interaction terms of DOE-RSM model upon the quadratic model of one-parameter variation to address the generalized case of simultaneous variations in multiple process parameters. The proposed methodology has been demonstrated for nand gate library with 266 gates, and the simplicity and generality of the approach make it equally applicable to a large library of cells for both statistical timing analysis and statistical circuit simulation at the gate level

Sub-25 nm UTB SOI SRAM cell under the influence of discrete random dopants

Intrinsic parameter fluctuations steadily increase with CMOS technology scaling. Around the 65 nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Device mismatch due to intrinsic parameter fluctuation causes each memory cell of the millions in a typical memory array to have different stability and performance. Ultra Thin Body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. Using a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into compact model, the impact of random discrete doping effects on 6T SRAM cell has been investigated for well scaled UTB SOI devices with physical channel length in the range of 10–5 nm. The impact of random doping in the source/drain regions of UTB SOI devices is quantified by changing the SRAM cell ratio and measuring the stability and performance during read and write operations. A comparison with the static noise margin characteristic of a 6T SRAM based on a conventional 35 nm MOSFET is also presented.

Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation

Novel device architectures such as ultra-thin body silicon-on-insulator (UTB SOI) MOSFETs which are more resistant to some of the sources of intrinsic parameter fluctuations are expected to play an increasingly important role beyond the 45 nm technology node. Apart from reduced device variability UTB SOI SRAM would benefit considerably from the superior electrostatic integrity and reduced junction capacitance compared to bulk MOSFETs. Furthermore, a steeper sub-threshold slope permits trade off between performance and power consumption for SRAM design. To fully realise performance benefits of UTB SOI based circuits a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into BSIMSOI compact model has been developed. The impact of body thickness variations on 6T SRAM static noise margins, read and write characteristics has been investigated for well scaled UTB SOI devices with physical channel length in the range of 10–5 nm.

Probabilistic Crosstalk Delay Estimation for ASICs

The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys normal distribution and its standard deviation is determined by the slew time of the victim along with the number of aggressor segments. The second is crosstalk delay normalized by the original delay without crosstalk, /spl Delta/t/sub pd//t/sub pd/. The /spl Delta/t/sub pd//t/sub pd/ is equal to 2*CPR at the maximum, and CPR on average, regardless of victim length. The two metrics in conjunction with empirical slew distribution allows us to set the appropriate crosstalk delay budget, at the prelayout stage, for reducing the possibility of the crosstalk violation found in the postlayout verification process.

Statistical device models from worst case files and electrical test data

Two statistical metal oxide semiconductors (MOS) models are described, one based on worst case files and the other on electrical test data. The former is appropriate for predicting the variability of a process early in its life cycle, while the latter would better track a maturing process. The key statistical tool that is used to develop the models is principal component analysis (PCA), which is used in novel ways in order to derive statistical models from readily available information. The models are used to perform statistical circuit simulation in order to quantitatively predict the impact of manufacturing variations on circuit performance metrics. Due to the use of linear response surface modeling and latin hypercube sampling, the simulation cost of using the models is about the same as with worst case simulation. The modeling technique is general and is applicable to other semiconductor devices besides MOS devices which are considered in this paper.

Statistical techniques for the computer-aided optimization of analog integrated circuit

A CAD tool capable of performing statistical circuit simulation, design, and optimization is described. The core of this tool is a general, CAD-compatible, statistical model which accounts for the effect of device area, transistor bias, and circuit layout on the variation of MOS integrated circuits. The statistical model has been incorporated into an object-oriented circuit simulator, APLAC, which has sufficient flexibility to allow optimization loops within a simulation input deck. The optimization of a two-stage operational amplifier, including the optimization of the standard deviation of the offset voltage, is performed using both steepest descent and constrained optimization techniques as an illustration of this statistical CAD tool. In this example, it is shown that the transistors which cause variations in op-amp circuit performance can be identified and resized in an area-efficient manner to meet a prescribed parametric circuit yield.

A physical and computationally efficient methodology for statistical circuit simulation in bipolar technologies

A methodology for statistical circuit simulation in advanced bipolar technologies is developed based on a novel IC TCAD system consisting of the semi-numerical mixed-mode device/circuit simulator MMSPICE with its parameter evaluator SUMM. The system reliably and efficiently relates device/circuit performance directly to measurable fabrication-process parameters since MMSPICE/SUMM implicitly accounts for physical correlations among device model parameters and does not rely on optimization (i.e. parameter extraction). The computational efficiency permits use of a simple Monte Carlo technique involving random generation of process parameters for the statistical simulation. The utility of the methodology is demonstrated by predicting IC parametric yields and statistical device/circuit performance correlations from specified fluctuations of process parameters in an actual bipolar technology.

A practical methodology for the statistical design of complex logic products for performance

Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their adaptive behavior, but at a substantial cost in computational effort. One practical solution to improving the accuracy of worst case design without sacrificing efficiency is considered here. It integrates an efficient statistical circuit simulator with worst case design tools into a hierarchical performance design process. It employs two stages of worst case analysis, calibrated with statistical circuit simulation, serving as filters to screen out circuits that easily meet their performance requirements. This focuses the use of statistical circuit simulation on those circuits for which the improved accuracy provides significant benefit. This methodology has been applied with outstanding results in design and manufacturing. >

A Statistical Model Including Parameter Matching for Analog Integrated Circuits Simulation

This paper describes a statistical model for circuit simulation that predicts variations in circuit behavior. This model includes parameter matching considerations critical to analog integrated circuits (IC's). The model is based on experimental data gathered from standard production bipolar-analog integrated chips. By using multivariate statistical techniques, the model is constructed having the two kinds of sub-models. One sub-model uses the eigenvalues and vectors of the correlation matrix, and then generates the correlation between devices on a chip. the other uses linear regression equations and generates the correlation within a device. The model has been implemented into a circuit simulator and statistical circuit simulations are performed. Measured device parameter variations in analog IC's are well reproduced within the practical execution time by the model. Simulation examples for analog IC's are demonstrated to illustrate the effectiveness of the model.

A statistical model including parameter matching for analog integrated circuits simulation

This paper describes a statistical model for circuit simulation that predicts variations in circuit behavior. This model includes parameter matching considerations critical to analog integrated circuits (IC's). The model is based on experimental data gathered from standard production bipolar-analog integrated chips. By using multivariate statistical techniques, the model is constructred having the two kinds of sub-models. One sub-model uses the eigenvalues and vectors of the correlation matrix, and then generates the correlation between devices on a chip. The other uses linear regression equations and generates the correlation within a device. The model has been implemented into a circuit simulator and statistical circuit simulations are performed. Measured device parameter variations in analog IC's are well reproduced within the practical execution time by the model. Simulation examples for analog IC's are demonstrated to illustrate the effectiveness of the model.

A GaAs 4 kbit SRAM with direct coupled FET logic

A GaAs 4-kb static RAM with enhancement/depletion direct coupled FET logic was designed and successfully fabricated by self-aligned implantation for n/SUP +/-layer technology (SAINT). The aim of the RAM circuit was to attain an access time of 2 ns with a power dissipation of less than 1 W. Statistical circuit simulation clarified the allowable scattering tolerance for FET threshold voltage of 45 mW. In-process monitoring was made wafer-to-wafer and chip-to-chip. A minimum address access time of 2.8 ns was measured with a power consumption of 1.2 W. Write and read operations were completely confirmed with a minimum write pulse width of 2 ns.