Standard Threshold Voltage Research Articles

Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology

The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%.

A 588 nW, 1 nA current reference circuit with extremely low (0.002%/V) line sensitivity over a wide supply voltage range and low temperature coefficient

AbstractA 1 nA current reference circuit is designed in semiconductor laboratory (SCL) 0.18 μm standard threshold voltage CMOS technology under 1.8 V power supply. The reference current is extremely immune to supply variation and shows a line sensitivity of 0.002%/V at post layout simulation level, over a wide range of supply variation from 0.5 V to 3.5 V. The line sensitivity is much smaller than any relevant data so far reported. In addition, it has a very low temperature coefficient of 214 ppm/°C over a temperature variation from −50°C to 50°C. The circuit consumes a total power of 588 nW. The reported results are also studied at various process corners and under variable process parameters like oxide thickness and threshold voltage of transistors. A satisfactory behaviour of the circuit is obtained in all cases. The accuracy of the simulation results is validated through quite close matching of the results with that obtained through rigorously developed theoretical models.

Characterization and Modeling of Native MOSFETs Down to 4.2 K

The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300K to 4.2K. The cryogenic Vth increases up to ~0.25V (W/L=10um/10um) and the improved subthreshold swing (SS)~14.30mV/dec@4.2K. The off-state current (Ioff) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different sub-bands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300K to 4.2K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.

A 2.1 ppm/°C, 0.55–2.4 V, 5.6 nW, 235 mV, CMOS-only subthreshold voltage reference

This study presents a high-precision, ultra-low-power, and CMOS-only subthreshold voltage reference. VPTAT with a positive temperature coefficient (TC) and VCTAT with a negative TC were generated to obtain a low-temperature dependence voltage reference. VPTAT was implemented using two standard-threshold voltage (STV) transistors working in the subthreshold region, while, VCTAT was implemented by a high-threshold-voltage (HTV) transistor and an STV transistor biased in the subthreshold region to obtain a ΔVGS with a negative TC. The voltage reference circuit was implemented via a standard 0.18-μm CMOS process with the core size around 0.022 mm2. The pre and post simulation results showed an average output reference voltage of around 235 mV with different supply voltages. Under a temperature range of −30 to 80 °C and the supply voltage of 0.55 V, the best TCs were as low as 2.1 and 7.6 ppm/°C for pre and post simulations, respectively. The total power consumption was only 5.6 nW when the supply voltage is 0.55 V.

Analysis, Design and Implementation of a Fully Integrated Analog Front-End for Microwave RFIDs at 5.8 GHz to Be Used With Compact MIMO Readers

In this paper we present the system and circuit level analysis and feasibility study of applying microwave Radio Frequency Identification (RFID) systems with multipleinput multiple-output (MIMO) reader technology for tracking machining tools in multipath fading conditions of production environments. In the proposed system the MIMO reader interrogates single-antenna tags, and a high RFID frequency of 5.8 GHz is chosen to reduce the size of the reader's antenna array. According to the requirements dictated by the performed system analysis at 5.8 GHz, a low power fully integrated analog frontend (AFE) is designed and fabricated in a standard 65-nm CMOS technology for low power passive transponders. Performance of the Differential Drive Rectifier (DDR) topology as the core of the energy harvesting unit is investigated in detail. A multi-stage DDR power scavenging unit is dimensioned to provide a 1.2 V rectified voltage for 20-30 kQ load range, with a high power conversion efficiency (PCE) for high frequency and low input power level signals. The rectified voltage is then converted to a 1 V regulated voltage for the AFE and the baseband processor with 30 to 50 μW of estimated power consumption. Transistors with standard threshold voltage (VT) have been used for implementation. Measurements of the fabricated multi-stage configuration of the circuit show a maximum PCE of 68.8% at -12.46 dBm, and an input quality factor (Q-factor) of approximately 10. Amplitude-shift keying (ASK) demodulator and backscattering modulator with 80% modulation index, operating according to EPC-C1G2 protocol are applied for data transfer. The AFE consumes less than 1 μW in the reading mode. The AFE tag chip is 0.55 × 0.58 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

High Performance ALU Using Carry Look-ahead Adder

A Low Power 8-bit Arithmetic Logic unit (ALU) using a Carry look-ahead adder (CLA) and placing Low Vt (LVt) cells in Critical path is anticipated. The ALU is designed in 90nm CMOS technology. ALU is the most essential circuit in any processor. It consists of AE, LE, CLA and CE. This ALU is designed to calculate Arithmetic and Logical operations. Power and Delay values of different 8-bit adders like CLA, Sparse and Ripple Carry Adder (RCA) are designed and compared. The simulation results show that the design of ALU using CLA and incorporating High Vt and Low Vt cells in the CLA gives more power and delay efficient than with only Standard threshold voltage cells.

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

SummaryProcess variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst‐case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low‐power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)‐level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Drain currents and their excess noise in triple gate bulk p-channel FinFETs of different geometry

The drain current I, spectral density of the low-frequency 1/f noise SI and transconductance gm of triple gate bulk p-channel field-effect transistors (FinFETs) fabricated on 200mm diameter Cz silicon wafers have been studied in the standard (ST) and Dynamic Threshold Voltage (DT) modes of operation. For the ST regime, a sub-linear increase of the drain current I with increasing overdrive voltage |Vov| and practically no changes in the spectral density SI of the noise are observed at high values of |Vov|. The effect is attributed to a sub-linear increase of the free hole density in the channel, whereby the mobility does not change with increasing |Vov|. An increase of the values of I, SI and gm normalized for the device geometry with increasing Leff is found and is attributed to the decrease of the mobility degradation coefficient with increasing Leff. For the DT regime of operation, the decrease of the threshold voltage |Vth| is not accompanied by an increase of the drain current which decreases with increasing |VGF| due to the high leakage current passing through the forward biased drain and source junctions. However, that decrease of the drain current is not accompanied by changes in the value of SI.

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

The impact of device width on the variability of radiation-induced leakage currents in 90nm and 65nm CMOS technologies is investigated. The off-state leakage current variability increases with decreasing channel width for both technologies, and with increasing total ionizing dose for three different process variants from the 90nm technology. More variability is observed for narrow width devices compared to wider devices before and after irradiation. Device-to-device variability is compared for two technologies (65 and 90nm) and three process variants (low, standard, and high threshold voltage). These results illustrate the importance of process-induced variability on the radiation response of MOS devices and integrated circuits.

The Role of High-Field Stress in the Negative-Bias Temperature Instability

In this paper, a fast drain-current measurement methodology which supports the standard threshold voltage and transconductance extractions associated with the fast dynamic negative-bias temperature instability (NBTI) is presented. Using this methodology, we show that production quality transistors exhibit only minimal degradation after a brief stress at moderate to high dielectric fields (contrary to the excessive degradation reported in the recent literature). The degradation at stress conditions which are consistent with many recent NBTI studies is shown to be dominated by high-field stress, instead of NBTI. The ability to extract transconductance from fast drain-current measurements helps to identify the existence of a latent electron trapping/detrapping component which provides further support of a degradation mechanism dominated by high-field stress. This high-field-stress component, while dominating, has not been accounted for in most of the recent NBTI literature.

Skew compensation in energy recovery clock distribution networks

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

Theory and application of dual-transistor charge separation analysis

The authors describe a dual-transistor charge separation method for evaluating the radiation response of MOS transistors. This method requires that n- and p-channel transistors with identically processed oxides be irradiated under identical conditions at the same oxide electric fields. Threshold voltage shifts due to oxide-trapped and interface-trapped charge are determined from standard threshold voltage and mobility measurements by combining features of single-transistor midgap and mobility methods. These measurements can be made at currents two-five orders of magnitude higher than those required for midgap, subthreshold slope, and charge-pumping methods. The dual-transistor method contains no adjustable parameters, and includes an internal self-consistency check. The accuracy of the method is verified by comparison to midgap, subthreshold slope, and charge-pumping methods for several MOS processes and technologies. Dual-transistor measurements and analysis not only provide a useful check of single-transistor analysis methods, but also may be the charge-separation method of choice for many applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dual-transistor method to determine threshold-voltage shifts due to oxide-trapped charge and interface traps in metal-oxide-semiconductor devices

A new technique is proposed to evaluate the radiation response of metal-oxide-semiconductor (MOS) transistors. The method requires that otherwise identical n- and p-channel transistors be irradiated under the same conditions. Using assumptions similar to those of widely accepted ‘‘single-transistor’’ methods, standard threshold-voltage and mobility measurements are combined to accurately estimate threshold-voltage shifts due to oxide-trapped charge and interface traps. This approach is verified for several MOS processes. The dual-transistor method can be applied to devices with much larger parasitic leakage, and at shorter times following a radiation pulse, than subthreshold current or charge-pumping techniques.

MOS Device Fabrication Using X‐Ray Lithography

X‐ray lithography has been applied to fabricate n‐MOS devices such as transistor matrixes, ring oscillators, and MOS capacitors. A propagation delay time as low as 200 psec/gate, and about 0.12 pJ power‐delay product were obtained from the ring oscillator with 0.7 μm effective gate length. From the threshold voltage measurements of the transistor matrixes, it was found that the standard threshold voltage deviation in MOSFET's with 1.5 μm effective gate length in a chip and the deviation in a wafer were as low as 5 and 7 mV, respectively.