Standard Surface Mount Technology Research Articles

Effect of environmental conditions on fracture behavior of solder joints

Double cantilever beam (DCB) specimens were prepared according to standard surface mount technology (SMT). The samples were stored inside an environmental chamber at two different relative humidity values (i.e. 40 or 100%) for either 2 or 4 h. Then they were aged at 25 °C, 75 °C or 125℃ for the same time. Finally, after being cooled to room temperature, fracture tests were performed under mode-I loading conditions at a strain rate of 0.03 s−1 at room temperature. Storage time did not have a significant effect on the fracture behavior. The fracture load and energy of the solder joints decreased significantly when the temperature was increased from 25 to 75℃. By further increase in the temperature from 75 to 125℃, the fracture strength slightly increased. This behavior was attributed to the thickness of intermetallic compound (IMC) as well as the portion of brittle phases on the joint microstructure. The influence of relative humidity on the fracture strength was less than the temperature effect due to coarsening behavior of microstructure with a humidity rise. The fracture surface of the specimen stored at a temperature of 25℃ and relative humidity of 40% was flat and smooth, while in other cases, the fracture surfaces showed a three-dimensional roughness.

Solder Immersion Process of Ceramic Column Grid Array Package Assembly for Space Applications

Ceramic column grid array (CCGA) packages are progressively being utilized for logic and microprocessor functionalities requiring very high-density interconnections. These packages offer various advantages, such as high reliability, good thermal and electrical performance, and reduced size and weight, due to which the use of these packages in space applications is becoming more and more popular. Assembly of such packages is always challenging for assembly and quality assurance engineers due to its post assembly inspection and rework limitations. These packages are usually assembled using the standard surface-mount technology (SMT) assembly processes involving solder paste printing on printed circuit boards (PCBs), component placement, and reflow soldering. An innovative tweak to the SMT process named solder immersion process (SImP) for assembly of CCGA is invented, where the solder paste is applied on the columns of the CCGA packages replacing the conventional solder paste printing/dispensing. SImP is useful for prototyping and reworkability and results in substantial improvement of the solder joint quality. This article explains the SImP in detail, test vehicle preparation, quality evaluation and subsequent accelerated thermal cycling test results, its applications, and advantages in the field of prototyping and reworkability.

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5- $\mu \text{m}$ lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than $15\times15$ mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances. To investigate board-level reliability, glass BGA packages, $18.5\times18.5$ mm2 in body size and 100 $\mu \text{m}$ in thickness, were first designed and fabricated with a daisy-chain pattern. The glass test vehicles were fabricated at panel level, and then BGA balled by ball drop process with SAC105 solder balls, 250 $\mu \text{m}$ in diameter at 400- $\mu \text{m}$ pitch. After singulation, the glass packages were mounted onto printed circuit boards using standard surface mount technology assembly processes, and then subjected to reliability testing through thermal cycling and drop tests following JEDEC reliability standards. The effect of the coefficient of thermal expansion (CTE) of glass was evaluated by investigating low- and high-CTE glass substrates, with the CTEs of 3.8 and 9.8 ppm/°C, respectively. While all glass packages passed 1000 thermal cycles at −40/125 °C as predicted by thermomechanical modeling using the Engelmaier–Wild model, the fatigue life of high-CTE samples exceeded 5000 thermal cycles. In addition, 28/30 drop-test samples passed the required 40 and 200 drops on corner and inner circuits, respectively, with no clear effect of the glass CTE. The predominant failure modes were systematically identified for both reliability tests.

Fracture load prediction of BGA solder joints: Cohesive zone modeling and experimental verification

• BGA test vehicles were prepared in a standard surface mount technology line. • Specimens with different geometries tested under various test configurations. • A strain-rate dependent cohesive zone model was developed. • The model was calibrated using one experimental data point. • The model was validated at arbitrary geometries and loading conditions. Ball grid array (BGA) test vehicles, assembled in a standard surface mount technology (SMT) line, were used to prepare fracture specimens in seven configurations in order to measure solder ball fracture loads at two different strain rate regimes for a range of loading mode ratios. The measured strengths of the specimens were compared with the predictions of a cohesive zone model (CZM). The phase angle of the specimens under bending was found to be close to mode I and hence the fracture criterion was governed predominantly by mode I parameters. The mode I peak stress and fracture energy of the CZM were obtained in two separate ways: (i) The fracture energy was obtained from separate copper-solder-copper double cantilever beam (DCB) tests, while the peak stress was obtained from one of the BGA specimen configurations. (ii) One BGA specimen configuration was used to obtain the mode I fracture energy, and the peak stress was assumed to be given by the yield stress. In both cases (i) and (ii), the rising slopes of the modes I and II traction-separation laws corresponded to the compliance of the system. The accuracy and generality of these CZ models was then assessed by using them to predict the fracture loads of the remaining BGA specimens that had different geometries and hence fracture strengths. The fracture loads predicted using either model were in reasonable agreement with the measured forces at a given strain rate. Therefore, once the CZM parameters have been defined for a given solder system using one BGA specimen, the CZM could predict the fracture of BGA solder joints with different geometries and strengths.

Nanocopper Based Solder-Free Electronic Assembly

CuantumFuse nano copper material has been used to assemble functional LED test boards and a small camera board with a 48 pad CMOS sensor quad-flat no-lead chip and a 10 in flexible electronics demo. Drop-in replacement of solder, by use of stencil printing and standard surface mount technology equipment, has been demonstrated. Applications in space and commercial systems are currently under consideration. The stable copper-nanoparticle paste has been examined and characterized by scanning electron microscopy and high-resolution transmission electron microscopy; this has shown that the joints are nanocrystalline but with substantial porosity. Assessment of reliability is expected to be complicated by this and by the effects of thermal and strain-enhanced coarsening of pores. Strength, creep, and fatigue properties were measured and results are discussed with reference to our understanding of solder reliability to assess the potential of this nano-copper based solder alternative.

Thermal effects in embedded thin- and thick-film resistors in comparison to chip resistors

Purpose – The purpose of this paper is to investigate the thermal behaviour of thin- and thick-film resistor with different dimensions and contacts embedded into printed circuit board (PCB) and compare them to the similar constructions of discrete chip resistors assembled to standard PCBs. Design/methodology/approach – In investigations the thin- and thick-film embedded resistors with the bar form in different dimensions and configurations of contacts as well as rectangular chip resistors in package 0603 and 0402 were used. In tests were carried out the measurements of dissipated power in temperature of resistor about 40°C, 70°C and 155°C. The power dissipation was calculated as a multiplying of electrical current flowing through the resistor with voltage across the resistor. The dissipation of heat generated by electrical current flowing through resistors was examined by means of the FLIR A320 thermographic camera with lens Closeup×2 and the power source. Findings – The results show that, in case of chip resistors, the intensity of heat radiation strongly depends on dimensions of copper contact lands and also depends on the dimensions of the resistor. In case of embedded resistors, with comparable dimensions to chip resistors, they have lower ability to power dissipation, as well as the copper contact lands dimensions have lower influence. The thermal radiation through resin material is not as effective as it is in case of resistors assembled on PCB. However, the embedded thick-film resistors, especially made of paste Minico M2010, have already the similar parameters to 0402 chip resistors. Research limitations/implications – Research shows that embedded resistors can be used interchangeably with SMD resistors it allows to open up space on the surface of PCB, but it should be taken into account the lower energy dissipation capabilities. It is suggested that further studies are necessary for accurately determining the thermal effects and investigate the structures of embedded passive components that allow for better heat management. Originality/value – Thermal stability of embedded resistors during operation is a critical factor of success of embedded resistor technology. The way of power dissipation and heat resistance are one of the important operating parameters of these components. The results provide information about the power and the energy dissipation of embedded thin- and thick-film resistors compared to the standard surface mount technology.

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.

X-ray imaging in pin-in-paste technology

Today, pin-in-paste technology is used extensively. With the help of pin-in-paste, through-hole devices can be soldered using a standard surface mount technology (SMT) process and hereby a reduction in wave soldering is possible. This can result in cost savings and a decrease in production cycle time. To ensure successful pin-in-paste soldering the following steps must be taken: solder paste volume calculations for through-hole components; stencil aperture design for the pin-in-paste application; solder paste deposition through stencil printing, application of solder volume increasing techniques after printing; reflow profile optimization; inspections using special methods for each individual process; final tests. The paste is printed into the through-holes. For high quality pin-in-paste solder joints a sufficient volume of paste is a fundamental requirement. Nevertheless, after printing the through-hole-filling is usually unknown. In this paper a new method is described how to accurately determine the volume of solder alloy in solder paste that is present in the through-hole, using X-ray measurements, image processing and calculations. In addition, a method is suggested to determine the measuring characteristics and gray-scale linearity of the X-ray machine.

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.

Flip Chip on Board: Assessment of Reliability in Cellular Phone Application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.

Large‐tolerant “OptoBump” interface for interchip optical interconnections

AbstractOptical interconnection technology for optical interboard and interchip connections will be an important technology in the next‐generation communication equipment seeking a high‐capacity throughput at the terabit per second level. With the objective of establishing an economical optical packaging technology, we propose an “optical I/O chip package,” which is an optical package for the hybrid integration of optoelectric (O/E) devices and LSI chips that can be mounted on a printed‐circuit board by standard surface mount technology (SMT). In this paper, we propose the OptoBump interface as the optical interconnection between the optical package and the board that connects these two elements by forming the microlens on both and using collimated light. Accommodating the fibers on the board and connecting the connectors become unnecessary because the connections having large beam diameters are able to tolerate offsets in the SMT mounting position. First, we calculated the required collimated beam diameter of 104 µm under the assumption of an SMT accuracy of ±50 µm. Next, we applied ray tracing to estimate the optical losses of the 45° mirror at the polymer optical waveguide facet integrated into the printed‐circuit substrate and clearly exhibited the incident beam conditions with both improved losses and tolerances. And we integrated the polymer microlens into the polymer optical waveguide and the surface‐emitting laser (VCSEL) and experimentally evaluated the optical coupling performance between them. The results verified a 1‐dB tolerance at ±50 µm and demonstrated the effectiveness of this proposal. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(1): 1–8, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10025

The development of reflowable materials systems to integrate the reflow and underfill dispensing processes for DCA/FCOB assembly

Unique materials systems with sufficient fluxing activities to remove the metal oxides on the die and/or substrate bumps and assist in the formation of metallurgical interconnects were developed for the assembly of flip chip on board (FCOB). This materials system is referred to as a reflowable underfill. The experimental process flow was as follows: a finite volume of reflowable underfill was dispensed on the printed circuit board (PCB) at the die site, the die was aligned over the bond pads, and the die was placed into the material. Next, the FCOB assembly was transferred to a reflow furnace and subjected to a standard surface mount technology (SMT) eutectic Pb/Sn reflow profile, the solder was reflowed, interconnects were formed between the die and PCB, and the reflowable underfill was partially cured. The built FCOB assemblies were placed in liquid to liquid thermal shock and air to air temperature cycling. The assembly yields varied and continued development of systems with increased flux activity are warranted for the acceptance of this FCOB assembling technology. Promising accelerated life testing (ALT) results were obtained warranting further evaluation of the reflowable materials systems and process.

Low-cost flip-chip on board

For hand-held communication products, like the DECT telephone system, flip-chip on board offers minimization of both the package size and the occupied area on the boards. As a result of the reduction in interconnection lengths, the self-inductance is reduced. For high volume production, the compatibility of the flip-chip mounting technique with standard surface mount technology (SMT) reflow is essential. During reflow, the eutectic PbSn bump wets along the copper track, so the stand-off between integrated circuits (IC's) and the board is accurately defined by the layout of the board and the dimensions of the bump. The eutectic PbSn flip-chip processing is evaluated by impedance and cross-talk measurements, and in several reliability tests. For the electrical measurements, a zero-IF front-end IC is used. Wide-band measurements of the input impedance showed that the residual parasitics associated with the eutectic PbSn bumps are negligible compared with the parameters of the internal IC components. To accommodate the residual stresses from differences in coefficient of thermal expansion (CTE), the gap between the IC and the substrate is underfilled. This underfill material marginally affects the electrical behavior of the IC at frequencies up to a few GHz. As expected, a slight increase in the residual capacitance is observed. The effect of the underfill is studied by both temperature cycle and shock tests; cumulative failure distributions have been plotted. Results show that the adhesion properties and flow characteristics of the underfill material are the dominating factors for the number of cycles to failure. By selecting the proper underfill and curing conditions, the eutectic PbSn flip-chip construction can meet the test requirements for consumer communication products.