Standard Deviation Of Cycle Time Research Articles

A New Stage-Wise Control Release Policy for Semiconductor Wafer Fabrication Systems

This article presents a new closed-loop release policy: Stage-Wise Control (SWC) that maintains the overall shop floor's workload distributed into stages at a specified level by controlling the release of new jobs along the production line A simulation model is developed for the well-known Mini Fab and a real-life fab to examine the potential advantage of SWC over traditional release policies in terms of the average cycle time, the standard deviation of cycle time, WIP level, the average number of tardy jobs, and throughput. The simulation results indicate that the SWC efficiently generates high-quality schedules for the average cycle time and the standard deviation of cycle time for a prescribed throughput level. Further, several simulation experiments are carried out in this study to understand the relative performance of SWC in comparison with the existing release policies with different dispatching rules, with different system variability levels caused by machine failure, and with different segmentation method. The performance of SWC is satisfactory in most of the considered scenarios compared to the tested release policies.

Experimental investigation for performance assessment of scheduling policies in semiconductor wafer fabrication—a simulation approach

This paper is concerned with assessing the impact of 15 existing release policies in combination with three dispatching rules (together called as scheduling policy) on the performance of semiconductor fabrication facilities using a simulation model of a representative but fictitious semiconductor wafer fab. The performance criteria employed includes average cycle time, standard deviation of cycle time, work in process (WIP) level, and throughput. Arena simulation software is used to build the simulation model and conduct the experimental study. The experimental results indicate that workload regulating (WR), constant work in process (CONWIP), and constant load (CONLOAD) policies are superior among tested release policies and shortest remaining processing time (SRPT) is the best dispatching rule. This paper present a new release policy called as constant workload (CONSTWL), which is a modified version of CONWIP policy to overcome the limitations of traditional release policies. CONSTWL policy triggers the release of job into the system based on the overall workload of shop floor. Results on computational experiments indicate that CONSTWL outperforms traditional release policies in terms of the average cycle time, the standard deviation of cycle time and work in process under a prescribed throughput level. The positive impact of CONSTWL policy on system performance appears to be reliable with the increase of system congestion level. CONSTWL policy may prove useful in practical contexts of make to stock manufacturing environment whose orders are met usually from finished inventory.

A fuzzy-neural and bi-objective scheduling system for job scheduling in a wafer fabrication factory

This paper established a fuzzy-neural and bi-objective scheduling system to improve the performance of job scheduling in a wafer fabrication factory. First, by controlling the standard deviation of cycle time, the fuzzy-neural and bi-objective scheduling system facilitates the rapid assignment of the internal due date. Subsequently, based on a precise cycle time estimation using a fuzzy back propagation network, the system attempts to assign a tight due date if more time is allowed. After the jobs related with an order are released into the wafer fabrication factory, a bi-objective dispatching rule is used to shorten cycle time standard deviation, and at the same time, to ensure on-time delivery, which is distinct from the previous studies because the existing dispatching rules in this field were not designed for such purposes. According to the experimental results, the proposed methodology is better than some existing approaches in both due date assignment and on-time delivery.

Impact of Production Control and System Factors in Semiconductor Wafer Fabrication

This paper validates a proposed job release methodology and experimentally investigates the impact of production control methodologies and system factors on wafer fab performance in terms of average cycle time, standard deviation of cycle time, average lateness, WIP inventory and fab output by simulating a wafer fab of Chartered Semiconductor Manufacturing Ltd (Chartered) and statistically analyzing the experimental results using t-test and ANOVA. A full factorial design of experiment is conducted to evaluate the performance of three job release methodologies, three dispatching rules and three greedy levels of batching policy under different system environmental settings differentiated by fab output level and machine unreliability level. Based on the experimental results, the proposed job release methodology WIPLOAD control (WIPLCtrl) appears to be very efficient to be able to potentially improve all the considered performance measures simultaneously. The advantage of WIPLCtrl is robust to the change of system environmental conditions. In contrast, the improvement brought by a dispatching rule on a certain performance measure might cost the deterioration of other performances. Considering the relative impact on the fab performance, job release control appears to be the most important production control factor in comparison with dispatching and batching policy, especially when the system is operating on a high output level and/or with a high system variability level caused by machine unreliability.

Dynamic state-dependent dispatching for wafer fabrication

A dynamic state-dependent dispatching (DSDD) heuristic for a wafer fabrication plant is presented. The DSDD heuristic dynamically uses different dispatching rules according to the state of a production system. Rather than developing new rules, the DSDD heuristic combines and modifies existing rules. This heuristic first classifies workstations into dynamic bottlenecks and non-dynamic bottlenecks. Dynamic bottleneck workstations apply a revised two-boundary dispatching rule when their queue length exceeds the average obtained from simulation using constant lot-release policy and first-in, first-out dispatching rule. Otherwise, the shortest expected processing time until next visit dispatching rule is used. A revised FGCA (FGCA+) dispatching rule is used for all non-dynamic bottlenecks workstations. Simulation results demonstrate that the DSDD heuristic obtains the best performance among the compared six dispatching rules in terms of average and standard deviation of cycle time and work-in-process.

Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants

The problem of reducing the mean and variance of cycle time in semiconductor manufacturing plants is addressed. Such plants feature a characteristic reentrant process flow, where lots repeatedly return at different stages of their production to the same service stations for further processing, consequently creating much competition for machines. We introduce a new class of scheduling policies, called Fluctuation Smoothing policies. Unanimously, our policies achieved the best mean cycle time and Standard Deviation of Cycle Time, in all the configurations of plant models and release policies tested. As an example, under the recommended Workload Regulation Release policy, for a heavily loaded Research and Development Fabrication Line model, our Fluctuation Smoothing policies achieved a reduction of 22.4% in the Mean Queueing Time, and a reduction of 52.0% in the Standard Deviation of Cycle Time, over the baseline FIFO policy. These conclusions are based on extensive simulations conducted on two models of semiconductor manufacturing plants. The first is a model of a Research and Development Fabrication Line. The second is an aggregate model intended to approximate a full scale production line. Statistical tests are used to corroborate our conclusions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>