Standard Active Pixel Sensor Research Articles

Hybrid UV Active Pixel Sensor Implemented Using GaN MSM UV Sensor and Si-Based Circuit

A hybrid active pixel sensor (APS) was implemented for ultraviolet (UV) imagers by combining a metal–semiconductor–metal (MSM)-type GaN UV sensor and a standard Si CMOS APS controller. The photodetector region of the APS circuit was replaced by a GaN MSM UV sensor, and it was connected together on the printed circuit board with standard Si CMOS APS circuit chip. The dark and photoresponsive current densities of the fabricated MSM UV sensor were $2.5 \times 10^{\mathrm {\mathbf {-6}}}$ and $1.6 \times 10^{\mathrm {\mathbf {-3}}}$ A/cm $^{\mathrm {\mathbf {2}}}$ , respectively, at 10 V bias. The fabricated hybrid UV APS has clearly distinguishable ON/OFF operation states under dark and 365-nm UV irradiation conditions. The calculated photoresponsivity of the hybrid-type GaN UV APS was as high as 5.1 V/W.

Lock-in Pixel Using a Current-Assisted Photonic Demodulator Implemented in 0.6 µm Standard Complemetary Metal–Oxide–Semiconductor

A complemetary metal–oxide–semiconductor (CMOS) lock-in pixel sensor based on a current-assisted photonic demodulation (CAPD) detector is described. The CAPD detector provides high demodulation contrast and yields excellent photo-response. The prototype followed standard active pixel sensor (APS) architecture and was fabricated using a 0.6 µm CMOS process from AMS. We obtained a near infrared (NIR) light responsivity of 0.26 A/W at 860 nm. The pixel exhibits demodulation contrast of nearly 100% at low frequencies and above 90% even up to 2 MHz. The phase response is linear up to 2 MHz, and even up to 10 MHz with the appropriate phase extraction equations.

Design, fabrication, and test of CMOS active-pixel radiation sensors

In this paper, we discuss some issues related to the design, implementation, and test of a CMOS active pixel sensor chip (RAPS01), developed in the framework of the radiation active pixel sensors (RAPS) INFN project. Two different basic pixel schemes have been proposed. The first one is based on a standard active pixel sensor (APS) architecture, while a second architecture, named weak inversion pixel sensor (WIPS) exploits a different circuitry which allows for "sparse" access mode and thus for speeding-up the readout phase. Chip fabrication has been completed and a preliminary test phase has been performed. A suitable test environment has been devised and test strategies have been planned. Preliminary test results, featuring a static and dynamic characterization of the basic sensitive elements are outlined. Future works are also outlined, aimed at the optimization of a second version of the chip, more effectively integrating smart circuitry.