Standard 1P6M Research Articles

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

A 1-V 4.6-μW/channel Fully Differential Neural Recording Front-end IC with Current-controlled Pseudoresistor in 0.18-μm CMOS

This paper presents a fully differential implantable neural recording front-end IC for monitoring neural activities. Each analog front-end (AFE) consists of a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a buffer. The output signal of the AFE is digitized through a successive approximation register analog-to-digital converter (SAR ADC). The LNA adopts the currentreuse technique to improve the current efficiency, achieving the power consumption as low as 0.95 μW. The implemented LNA has the gain of 40 dB, the lowpass cutoff frequency of 10 kHz, and the high-pass cutoff frequency of sub-1 Hz which is realized using the current-controlled pseudoresistor. The VGA controls the gain from 21.9 dB to 33.9 dB for efficient digitization while consuming the power of 0.35 μW. The buffer drives the capacitive DAC of the ADC and consumes the power of 3.28 μW. The fabricated AFE occupies the area of 0.11 ㎟/Channel and consumes 4.6 μW/Channel under 1-V supply voltage. Each channel achieves the input-referred noise of 2.88 μVSUBrms/SUB, the NEF of 2.38, and the NEF²VSUBDD/SUB of 5.67. The front-end IC is implemented in a standard 1P6M 0.18-mm CMOS process.

Pixel-level A/D conversion using voltage reset technique

This paper presents a 50 Hz 15-bit analog-to-digital converter (ADC) for pixel-level implementation in CMOS image sensors. The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets. The core circuit for charge/pulse conversion is specially optimized for low power, low noise and small area. An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification. The measurement result shows a standard deviation of 1.8 LSB for full-scale output. The ADC has an area of 45 × 45 μm2 and consumes less than 2 μW in a standard 1P-6M 0.18 μm CMOS process.

A 400-MS/s 12-bit current-steering D/A converter

This paper presents a 400-MS/s 12-bit CMOS current-steering digital-to-analog converter (DAC). The proposed DAC adapts 6+2+4 segmented architecture and a modified switching scheme to improve dynamic and static performance. The measured spurious-free dynamic range is up to 77.18 dB at 400 MS/s with a 10 MHz input signal. The full-scale output current is 20 mA with a 1.8 V single power supply. The core area occupies 0.6 mm2 in a standard 1P-6M 0.18-μm CMOS process.

A 30.8-dBm Wideband CMOS Power Amplifier With Minimized Supply Fluctuation

A wideband design method for a twisted eight-shape transformer is introduced with the design guidelines. The supply modulation effect caused by the fluctuation of virtual ground is analyzed. To minimize the effect, the different matching capacitors are adopted at each port and an accurate virtual ground is positioned. For verification, a fully integrated linear CMOS power amplifier (PA) is implemented in a 0.18-μm standard 1P6M RF CMOS process for 2.3- and 2.6-GHz m-WiMAX (IEEE 802.16e standard) system. In continuous-wave measurements, the two-stage Class-AB PA delivers 30.8-dBm saturated power with a 30.6% power-added efficiency (PAE) and 22-dB gain across 900-MHz bandwidth (defined as 1-dB gain bandwidth). In 16 quadrature amplitude modulation m-WiMAX modulation signal measurements, the PA generates 26.2-dBm average power with a 20.5% PAE. The PA complies with the spectrum mask at a 21-dBm average power level and satisfies 3% error vector magnitude at 17-dBm average power.

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection

Conventional binary-weighted current-steering DACs are generally operated with current groups where each group is binary-weighted and formed with predetermined members of a unit current-source array. This paper proposes a random rotation-based binary-weighted selection (RRBS) that efficiently performs dynamic-element matching (DEM) by randomly rotating the sequence of these units to form new binary-weighted current groups for each DAC output. Without using binary-to-thermometer decoders, RRBS features its simplicity and compactness of DEM realization. Compared to conventional binary-weighted DACs, RRBS DACs are insensitive to the mismatch of small-size current-sources and exhibit better dynamic performance. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a standard 1P6M 1.8 V 0.18 μm CMOS process. Measured performance achieves >;61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10-12-bit DACs, with the proposed design performing best with 2 FOMs.

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm2, among which the area of the current-source block is only 0.28 mm2. The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.