Stage OTA Research Articles

Design of Two stage OTA with Optimised Compensation Capacitance

A two-stage operational transconductance amplifier is constructed and compared between 45nm and 180nm CMOS technology in this paper. To find the best design, the suggested operational amplifier is examined across a number of distinct parameters. With a supply voltage of 1.8V, it reaches a maximum gain of about 66 dB and a phase margin of 82°. A Cadence Virtuoso-based circuit simulator has been used to construct the suggested operational amplifier and the comparison is done. Keywords: OTA, Miller coupling capacitance, cadence virtuoso, Gain, output swing, power dissipation.

A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA

This article describes a highly energy-efficient Wheatstone bridge temperature sensor. To maximize sensitivity, the bridge is made from resistors with positive (silicided diffusion) and negative (poly) temperature coefficients. The bridge is balanced by a resistive (poly) FIR-DAC, which is part of a 2nd-order continuous-time delta-sigma modulator (CTΔΣM). Each stage of the modulator is based on an energy-efficient current-reuse OTA. To efficiently suppress quantization noise foldback, the 1st stage OTA employs a tail-resistor linearization scheme. Sensor accuracy is enhanced by realizing the poly arms of the bridge and the DAC from identical unit elements. Fabricated in a 180-nm CMOS technology, the sensor draws 55 μW from a 1.8-V supply and achieves a resolution of 150 μKrms in an 8-ms conversion time. This translates into a state-of-the-art resolution figure-ofmerit (FoM) of 10 fJ·K2. Furthermore, the sensor achieves an inaccuracy of ±0.4 °C (3σ) from -55 °C to 125 °C after a ratio-based one-point trim and systematic non-linearity removal, which improves to ±0.1 °C (3σ) after a 1st-order fit.

A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain

This brief proposes a 0.25V rail-to-rail three stage OTA. The proposed OTA improves a DC gain by inserting an NMOS gate-driven amplifier into the conventional bulk-driven OTA. In addition, it uses an asymmetric self-cascode transistor and an indirect feedback compensation to enhance a DC gain and an unit-gain frequency. At the first stage, the bulk-driven amplifier has a rail-to-rail input, but it has a low DC gain due to a small transconductance. At the second stage, the NMOS gate-driven amplifier enhances the DC gain. At the last stage, the common-source amplifier drives an output load capacitor. The proposed OTA was fabricated using a 65nm CMOS process. Its area is 0.002mm2. It consumes $0.026~\mu \text{W}$ at the supply-voltage of 0.25V. The DC gain and unit-gain frequency are 70dB and 9.5kHz, respectively, with the phase margin of 88° at the load capacitance of 15pF.

Four stage OTA CMOS frequency compensation based on double differential feedback paths

Multi-stage amplifiers become logical choices for high-speed electronics and data conversion. The main difficulty in design is performing frequency compensation due to increasing high impedance nodes. In this work, a four-stage CMOS amplifier is frequency compensated using double differential feedbacks paths. Only two small compensation capacitors, less than 1 pF are used to form four Miller loops and driving a 500 pF load capacitor. The transfer function is calculated and simplified to estimate circuit dynamics while HSPICE and TSMC 0.18 µm CMOS technology are used to simulate the proposed four-stage amplifier. According to simulations and mathematical description, the proposed structure shows 147 dB, 6.3 MHz and 85° as DC gain, GBW, and PM respectively while consumes 380 µW as power dissipation. According to the defined figure of merits, the proposed circuit shows performance excellency against the previous state of art designs.

Multi stage OTA design: From matrix description to circuit realization

This paper presents a comprehensive approach to frequency compensating multistage amplifiers. Different stage cases have been considered namely, differential voltage and current blocks, and general compensation blocks for both voltage and current states. Then, a matrix description has been proposed to describe the configurations. The approach involved binary matrixes in order to model amplifiers with feedback networks. Evolutionary algorithms were used to find optimum numerical values and simplify symbolic transfer functions. Also a diagram-based design was used to find the appropriate MOSFET DC bias conditions and dimensions. Note that using simplified transfer functions to symbolically locate the poles and zeroes allowed a better circuit design knowledge compared to numerical approaches. To demonstrate the proposed procedure, two circuit were designed in TSMC 0.18 μm CMOS technology and simulated results successfully compared to linear models extracted from the matrix description. According to simulations, the proposed configurations in both voltage and current states show excellence performance versus previous works. Finally, special design cases such as multi-compensation blocks and N-stage approach were discussed.

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

A 1.1 mW 87 dB dynamic range Δ σ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order Δ σ modulator implemented in 0.18 μm CMOS technology for audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed. A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.