Nanowire Stacks Research Articles

Integrated α-MnO2 nanowires PVDF catalytic membranes for efficient purification of dye wastewater with high permeability

Catalytic membranes have been studied and reported widely, but ideal catalytic membranes with high rejection ratio and high permeability simultaneously are still a challenge to develop. Herein, integrated α-MnO2 nanowires polyvinylidene fluoride (PVDF) catalytic membranes were fabricated by a vacuum filtration method. Based on the intercalation structures of GO formed by α-MnO2 nanowires and the spatial stacking of nanowires, filter channels with high water flux were constructed. While CS displayed as anchor point to fix α-MnO2 nanowires and also endow the membrane surface with electro-positivity. Then, a sequence of catalytic membranes with different content of α-MnO2 were prepared, and detailed characterizations of structure were taken out. Finally, all of the membranes displayed excellent stability in harsh conditions (pH values from 3 to 11), and M-5 with the most content of α-MnO2 displayed the best separation ability, for which the rejection ratio reached 99.26 % along with a high permeability about 923.72 L·m−2·h−1·Bar−1, when it was used to separate methyl blue (MBE) wastewater. In addition, M-5 also displayed excellent reusability, such as the rejection ratio still maintained above 92.62 % after 9th cycles and reduced to 86.74 % after 10th cycle, while the permeability still remained 612.09 L·m−2·h−1·Bar−1 after the 10th cycle. Therefore, this work developed an outstanding catalytic membrane, which displayed good application prospect for treatment of dye wastewater.

Synthesis of orthogonally assembled 3D cross-stacked metal oxide semiconducting nanowires.

Assemblies of metal oxide nanowires in 3D stacks can enable the realization of nanodevices with tailored conductivity, porous structure and a high surface area. Current fabrication methods require complicated multistep procedures that involve the initial preparation of nanowires followed by manual assembly or transfer printing, and thus lack synthesis flexibility and controllability. Here we report a general synthetic orthogonal assembly approach to controllably construct 3D multilayer-crossed metal oxide nanowire arrays. Taking tungsten oxide semiconducting nanowires as an example, we show the spontaneous orthogonal packing of composite nanorods of poly(ethylene oxide)-block-polystyrene and silicotungstic acid; the following calcination gives rise to 3D cross-stacked nanowire arrays of Si-doped metastable ε-phase WO3. This nanowire stack framework was also tested as a gas detector for the selective sensing of acetone. By using other polyoxometallates, this fabrication method for woodpile-like 3D nanostructures can also be generalized to different doped metal oxide nanowires, which provides a way to manipulate their physical properties for various applications.

Series Resistance Reduction With Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency (RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance ${g}_{m\textsf {2}}$ and ${g}_{m\textsf {3}}$ . These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET.

Influence factors of the inter-nanowire thermal contact resistance in the stacked nanowires

The inter-nanowire thermal contact resistance is important for tuning the thermal conductivity of a nanocomposite for thermoelectric applications. In this paper, the stacked copper nanowires are applied for studying the thermal contact resistance. The stacked copper nanowires are firstly made by the cold-pressing method, and then the nanowire stacks are treated by sintering treatment. With the effect of the volumetric fraction of nanowires in the stack and the influence of the sintering-temperature on the thermal contact resistance discussed, results show that: The thermal conductivity of the 150-nm copper nanowires can be enlarged almost 2 times with the volumetric fraction increased from 32 to 56% because of the enlarged contact-area and contact number of a copper nanowire. When the sintering temperature increases from 293 to 673 K, the thermal conductivity of the stacked 300-nm nanowires could be enlarged almost 2.5 times by the sintering treatment, because of the improved lattice property of the contact zone. In conclusion, application of a high volumetric fraction or/and a sintering-treatment are effectivity to tune the inter-nanowire thermal contact resistance, and thus to tailor the thermal conductivity of a nanowire network or stack.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current. In this paper, we show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. It is found that upscaling the diameter of lower nanowires with respect to the upper nanowires improved uniformity of the current in each nanowire, but with the drawback of threshold voltage reduction. We propose to increase source/drain trench silicide depth as a more promising solution to this problem over the nanowire diameter scaling, without compromising on power or performance of these devices.

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- $V_{\rm th}$ optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power.

3D Hybrid Plasmonic Nanomaterials for Highly Efficient Optical Absorbers and Sensors.

3D hybrid plasmonic nanomaterials are composed of 3D-stacked Ag nanowires and nanoparticles separated by a nanoscale-thick alumina interlayer. The 3D hybrid plasmonic nanostructures exhibit strong plasmonic coupling between the ultrahigh populations of plasmonic nanomaterials, overcoming the physical limitation of inefficient plasmonic coupling of the Ag nanowire stacks.

Design of Nanowire Optical Cavities as Efficient Photon Absorbers

Recent investigations of semiconductor nanowires have provided strong evidence for enhanced light absorption, which has been attributed to nanowire structures functioning as optical cavities. Precise synthetic control of nanowire parameters including chemical composition and morphology has also led to dramatic modulation of absorption properties. Here we report finite-difference time-domain (FDTD) simulations for silicon (Si) nanowire cavities to elucidate the key factors that determine enhanced light absorption. The FDTD simulations revealed that a crystalline Si nanowire with an embedded 20-nm-thick amorphous Si shell yields 40% enhancement of absorption as compared to a homogeneous crystalline Si nanowire, under air-mass 1.5 global solar spectrum for wavelengths between 280 and 1000 nm. Such a large enhancement in absorption results from localization of several resonant modes within the amorphous Si shell. A nanowire with a rectangular cross section exhibited enhanced absorption at specific wavelengths with respect to a hexagonal nanowire. The pronounced absorption peaks were assigned to resonant modes with a high symmetry that red-shifted with increasing size of the rectangular nanowire. We extended our studies to investigate the optical properties of single- and multilayer arrays of these horizontally oriented nanowire building blocks. The absorption efficiency of a nanowire stack increases with the number of nanowire layers and was found to be greater than that of a bulk structure or even a single nanowire of equivalent thickness. Lastly, we found that a single-layer nanowire array preserves the structured absorption spectrum of a single nanowire and ascribed this result to a diffraction effect of the periodic nanowire array. The results from these provide insight into the design of nanowire optical cavities with tunable and enhanced light absorption and thus, could help enable the development of ultrathin solar cells and other nanoscale optoelectronic devices.

Transient Response of 3-D Multi-Channel Nanowire MOSFETs Submitted to Heavy Ion Irradiation: a 3-D Simulation Study

The single-event response of 3-D Multi-Channel nanowire MOSFETs (MCFET) is investigated using 3-D numerical simulation. The variation with time of the main internal parameters (electrostatic potential and electron density) of the MCFET after the ion strike is analyzed in detail. The drain current transients and collected charge depend on the ion strike location, direction, and track radius. The lateral spacing between adjacent nanowire stacks is found to be a key-parameter in the analysis of the worst case location of the ion strike.

Fabrication of Suspended Ge-rich Nanowires by Ge Enrichment Technique for Multi-channel Devices

This paper presents a new top-down method to fabricate Ge-rich nanowires for multi-channel devices by Ge enrichment technology. 3 dimensional Ge nanowire stacks have been fabricated and characterized by SEM, TEM, EDX. Nanowires obtained are single crystalline with no crystalline defects observed on cross-sectional TEM pictures. The main advantage of this method is that the shape, the size and the concentration of Ge nanowires can be tuned by process parameters. Indeed, depending on these parameters, nanowires with a Ge content up to 100% can be obtained with a very aggressive diameter (as low as 10nm). Moreover, this technology allows the co-integration of Ge and Si nanowires for pMOS and nMOS devices, respectively.

The effect of the hydrothermal treatment with aqueous NaOH solution on the photocatalytic and photoelectrochemical properties of visible light-responsive TiO 2 thin films

The effect of the hydrothermal treatment with aqueous NaOH solution on the photoelectrochemical and photocatalytic properties of visible light-responsive TiO 2 thin films prepared on Ti foil substrate (Vis-TiO 2/Ti) by a radio-frequency magnetron sputtering (RF-MS) deposition method has been investigated. The hydrothermally treated Vis-TiO 2/Ti electrodes exhibited a significant increase in their photocurrent under UV and visible light irradiation as compared to untreated Vis-TiO 2/Ti electrode. SEM investigations revealed that the surface morphology of Vis-TiO 2/Ti are drastically changed from the assembly of the TiO 2 crystallites to the stacking of nanowires with diameters of 30–50 nm with increasing hydrothermal treatment time (3–24 h), accompanying the increase in their surface area. The separate evolution of H 2 and O 2 from water under solar light irradiation was successfully achieved using the Vis-TiO 2/Ti/Pt which is hydrothermally treated for 5 h, while the H 2 evolution ratio was 15 μmol h −1 in the early initial stage, corresponding to a solar energy conversion efficiency of 0.23%.