Stacked Gate Oxide Research Articles

Sensitivity analysis of bi-metal stacked-gate-oxide hetero-juncture tunnel fet with Si0.6Ge0.4 source biosensor considering non-ideal factors.

This article provides insights in designing a dielectrically modulated biosensor by adopting high-k stacked gate oxide proposition in a bi-metal hetero-juncture Tunnel Field Effect Transistor (BM-SO-HTFET) with Si0.6Ge0.4 source. The integrated effect of heterojunction and stacked gate oxide leads to enhanced electrical performance of the proposed device in terms of carrier mobility and suppressed leakage current. Nano-cavity engraved beneath the bi-metal gate structure across the source/channel end acts the binding site of the biomolecules to be detected. This Configuration leads to improved control of biomolecules over source/channel tunnelling rate and the same is reflected in the sensing ability of the device while extracting the ON current sensitivity (SON) of the sensor. The reported biosensor is simulated using Silvaco ATLAS calibrated simulation framework. The analysis of the device sensitivity is carried out varying dielectric constants (k) of various biomolecules, both neutral as well as charged. Our study reveals that BM-SO-HTFET with Ge mole fraction composition x = 0.4 exhibits sensitivity as high as 4.1 × 1010 for neutral biomolecules and 3.2 × 1011 for positively charged biomolecules with k = 12. Furthermore, a transient response profile for the drain current with various biomolecules is explored to determine the varying settling time. From the simulation results, it is noted that BM-SO-HTFET exhibits ON current sensitivity of 4.1 × 1010 and 3.2 × 1011 for neutral and charged biomolecules respectively. In addition to this, for highly sensitive and real time detection of biomolecules, the impact of temperature and certain non-ideal factors drifting from ideal case of fully filled cavity have also been considered to analyze its optimum sensing performance.

A new stacked gate oxide L-shaped tunnel field effect transistor

A new stacked gate oxide L-shaped tunnel field effect transistor

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56 × 10−5 A μm−1, which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635 × 10−12 A/μm. The simulation of the device is carried out with optimization of the doping to investigate and improve the device’s performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

Performance Enhancement of Three Fins Vertically Stacked Quad Gate Nanosheet by Employing Rectangular Core–Shell, Doping and Gate-Dielectric Engineering

A Rectangular core–shell (RCS), employed to three fins vertically stacked with gate oxide stack junctionless nanosheet, along with doping and gate/dielectric engineering, is explored. This paper proposes an N-type three fins vertically stacked with gate oxide stack junctionless nanosheet with opposite core doping in the channel referred to as RCS. The simulation results show that three fins vertically stacked with gate oxide stack with RCS junctionless nano-sheet exhibit reduced Ioff is 6.913E-21, increased Ion is 2.408E-07, Ion/Ioff ratio is 0.418×106, DIBL is 6.9mV and SS is 60.65 mV/dec, respectively. Furthermore, the P-type of three fins vertically stacked with gate oxide stack junctionless nanosheet and combined -type and P-type three fins vertically stacked with gate oxide stack junctionless nano-sheet were stimulated to construct the inverter circuit. The Voltage Transfer Characteristics (VTC) of three fins vertically stacked with gate oxide stack junctionless nano-sheet with RCS have HfO2 as the gate-oxide based inverter has been notably improved compared to SiO2, al2O3 as a gate oxide and conventional three fins vertically stacked with gate oxide stack junctionless nano-sheet inverter.

TID response of hybrid FinFET with modified gate dielectric

The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose.

Low-frequency noise in InSnZnO thin film transistors with high-quality SiO2 gate oxide stacks

Low-frequency noise (LFN) in InSnZnO (ITZO) thin-film-transistors (TFT) with high-quality SiO2 gate oxide (GO) stacks is studied. This stack is fabricated by the plasma enhanced chemical vapor deposition (PECVD) and comprises two single layers. One layer is deposited by a SiH4 source (SiH4–SiO2), and the other uses a tetraethyl-orthosilicate precursor (TEOS-SiO2). The drain current noise power spectral densities follow the typical 1/f rule, and the main origin of LFN changes with the variation of drain current intensities. At low drain current intensities, LFN is affected by grain boundaries in the channel. As the drain current intensities increase, LFN originates from the carrier number fluctuations in devices with single TEOS-SiO2 GOs and from the carrier number with correlated mobility fluctuations in devices with SiO2 stacks GOs. At extremely high drain current intensities, the contact noise acts as a significant source of LFN in devices with SiO2 GO stacks. According to the carrier number with correlated mobility fluctuation (ΔN−Δμ) model, the devices with optimal stacks GOs exhibit a relatively low trap density near the ITZO/SiO2 interface. Additionally, these devices have a lower border trap density in GOs compared to those with single compositions. It demonstrates that high-quality SiO2 stacks reduce traps near the SiO2/ITZO interface, leading to enhanced devices performance. This work provides a precise and efficient method to evaluate the quality of GOs in metal oxide TFTs.

Improvements in reliability and radio frequency performance of junctionless tunnelling field effect transistor using p+ pocket and metal strip

AbstractIn this article, a new p+ pocket stacked gate oxide junctionless tunnelling field effect transistor (junction less tunnelling field effect transistor (JLTFET)) which has metal strip in gate oxide layer is proposed for analogue/RF circuit applications. Due to the insertion of a p+ pocket in source/channel junction and the use of metal strip in oxide layer, the following properties of the proposed JLTFET are resulted. First, the tunnelling barrier width is reduced in the source/channel junction thereby, electrons easily tunnel from the source to the channel. Second, the hole concentration (empty state) in the channel is increased, leading to higher electron contribution in the tunnelling process. These improvements are useful in achieving high drain current and steep subthreshold swing. As a result, the maximum ON current of 4.4 × 10−5 A/μm and average subthreshold swing of 40 mV/decade are obtained from simulation results. Moreover, as compared to conventional JLTFET, the proposed JLTFET provides improvements in reliability and analogue/radio frequency (RF) performance.

Simultaneously-doping of HfO2 thin films by Ni with sputtering technique and effect of post annealing on structural and electrical properties

This article reports a detailed structural and electrical characterization study of Ni:HfO2 dielectrics grown by rf and dc sputtering and variations in the rapid thermal annealing temperature. Annealing produced obvious changes in the morphological structure of films and XRD confirmed that the crystallite size increased from 1.3 nm to 14.4 nm with the annealing temperature. XPS showed that the amount of non-lattice oxygen decreased owing to the effects of annealing and resistivity. Dc resistivity measurements showed that the lowest sheet resistance of 1.182 × 106 Ω/□ was achieved by as-deposited films and increased to 70.960 Ω/□ with annealing. Structural differences in films due to the effect of annealing caused equivalent circuit models to vary and different resistance values in electrochemical impedance spectrometry. This study illustrates that HfO2 thin films, boosted by doping and rapid thermal annealing, provide a route toward advanced gate oxide stack structures in electronic devices beyond conventional high-dielectric-constant materials.

Ferroelectric Nanopillar Field-Effect Transistors: Quantum Transport Simulations Based on a Three-Dimensional Phase Field

A ferroelectric field-effect transistor (FEFET) with a cylindrical ferroelectric (FE) nanopillar embedded in the gate oxide stack is proposed and investigated. The device utilizes the multiple polar topological states, which can be stabilized in a nanoscale regime. To correctly simulate the proposed FEFET, a full three-dimensional phase-field-based quantum transport model is developed where nonequilibrium Green's function, Poisson, and time-dependent Ginzburg-Landau equations are self-consistently solved. Using the in-house tool, we theoretically demonstrate that the nanopillar FEFET exhibits multibit operation of six-level states with a reasonable memory window (MW) and sufficiently large difference in the current between the states. We also investigate the short-channel effect on the proposed FEFET and assess its scalability. MW linearly increases as the gate length decreases, because the polarization bound charges of the FE nanopillar induce the quasi-bound-states on the channel region and thus degrade the gate controllability.

Quantum Effect Dependent Modelling of Short Channel Junctionless Double Gate Stack(SC-JL-DG) MOSFET for High Frequency Analog Applications

In this paper, the quantum effect has been induced on Junctionless (JL)-Double Gate metal-oxide-semiconductor field-effect transistors (JL-DGMOSFET) with gate oxide stack to study its effect on different device parameters like surface potential, threshold voltage, Id, Vg, gm, channel length etc. The study has been extended on Ion/Ioff change w.r.t. the variation in spacer width for varied channel thickness. In order to extend the efficacy of the results an analytical model has been formulated. The analytical model is developed by incorporating the Schrodinger equation in the conventional 2-D Poisson's equation, which has further been solved by applying the boundary conditions to obtain the final expression for potential and change in threshold voltage (Vth). The device parameters are in accordance for both the simulated and analytical results. The simulation work has been supported by the ATLAS device simulation.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

The relationship among the on-to-off current ratio, threshold voltage, and the gate metal work-function is investigated for a junctionless (JL) Gate-All-Around (GAA) MOSFET with a gate oxide film in which SiO2 and a high-k dielectric material are stacked. The JL structure works in the accumulation state, and the threshold voltage is defined as the gate voltage when the minimum potential in the channel becomes Fermi potential. The on-to-off current ratio Ion/Ioff is obtained by obtaining on-current Ion at the threshold voltage and off-current Ioff at the gate voltage of 0 V. As a result, if the channel doping concentration and silicon radius are increased to reduce the channel resistance, the on-to-off current ratio decreases along with the threshold voltage, but this problem can be solved through the increasing of the gate metal workfunction. In addition, even when the relative permittivity of the high-k dielectric is increased from 3.9 to 20, the gate metal work-function to maintain any on-to-off current ratio and threshold voltage is very slightly changed. Therefore it will be possible to improve the controllability of the gate by increasing the permittivity of the high-k dielectric without change in the work-function. The reduction of the channel resistance of the JL GAA MOSFET is possible with the stacked gate oxide while maintaining a reasonable on-to-off current ratio and threshold voltage by adjusting the gate metal work-function

Design and investigation of InAs source dual metal stacked gate-oxide heterostructure tunnel FET based label-free biosensor

In this paper, a stacked gate oxide (high-k/low-k) approach towards the design of a Dual Metal Stacked Gate oxide Heterostructure Tunnel Field Effect Transistor (DM SGox HTFET) dielectric modulation-based biosensor is presented. A direct band-gap material, Indium Arsenide (InAs) has been selectively grown in the source region on silicon to create a heterostructure to achieve improved mobility of charge carriers in the TFET structure. The sensitivity of the biosensor is evaluated for varied neutral and charged biomolecules of different dielectric constants (k). The 2D simulation has been simulated in SILVACO ATLAS TCAD tool. Due to the stacked gate oxide architecture under the nano-gap, the immobilized biomolecules are stabilized in the nano-gap and reduction of leakage current is maintained effectively which gives rise to an impressive ON current sensitivity. The proposed device structure exhibits an increase of approximately ten orders of magnitude of ON current sensitivities for both neutral and positively charged gelatin biomolecules in comparison to the previous works in the literature.

Performance Investigation of Ge Based Pocket Doped TMSG-TFET with a SiO2/HFO2 Stacked Gate Oxide Structure for Enhanced Drain Current for Low Power Applications

Performance Investigation of Ge Based Pocket Doped TMSG-TFET with a SiO2/HFO2 Stacked Gate Oxide Structure for Enhanced Drain Current for Low Power Applications

Ultrathin ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental changein the gate stack in 2008,the incorporation of high-dielectric-constant HfO2(ref.2), which remains the material of choiceto date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Sub-Nanometer Interfacial Oxides on Highly Oriented Pyrolytic Graphite and Carbon Nanotubes Enabled by Lateral Oxide Growth.

A new generation of compact and high-speed electronic devices, based on carbon, would be enabled through the development of robust gate oxides with sub-nanometer effective oxide thickness (EOT) on carbon nanotubes or graphene nanoribbons. However, to date, the lack of dangling bonds on sp2 oriented graphene sheets has limited the high precursor nucleation density enabling atomic layer deposition of sub-1 nm EOT gate oxides. It is shown here that by deploying a low-temperature AlOx (LT AlOx) process, involving atomic layer deposition (ALD) of Al2O3 at 50 °C with a chemical vapor deposition (CVD) component, a high nucleation density layer can be formed, which templates the growth of a high-k dielectric, such as HfO2. Atomic force microscopy (AFM) imaging shows that at 50 °C, the Al2O3 spontaneously forms a pinhole-free, sub-2 nm layer on graphene. Density functional theory (DFT) based simulations indicate that the spreading out of AlOx clusters on the carbon surface enables conformal oxide deposition. Device applications of the LT AlOx deposition scheme were investigated through electrical measurements on metal oxide semiconductor capacitors (MOSCAPs) with Al2O3/HfO2 bilayer gate oxides using both standard Ti/Pt metal gates as well as TiN/Ti/Pd gettering gates. In this study, LT AlOx was used to nucleate HfO2 and it was shown that bilayer gate oxide stacks of 2.85 and 3.15 nm were able to achieve continuous coverage on carbon nanotubes (CNTs). The robustness of the bilayer was tested through deployment in a CNT-based field-effect transistor (FET) configuration with a gate leakage of less than 10-8 A/μm per CNT.

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

<span>The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO<sub>2</sub>/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. </span><span>The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10<sup>4</sup> or less is shown for SiO<sub>2</sub>, but the on-off current ratio for TiO<sub>2</sub> (<em>k</em>=80) increases to 10<sup>7</sup> or more.</span>