Dielectric Stack Research Articles

Charge trapping gate stack enabled non-recessed normally off AlGaN/GaN HEMT with high threshold voltage stability

This paper reports a non-recessed normally off AlGaN/GaN high-electron-mobility transistor (HEMT) with a charge trapping gate dielectric stack. The charge trapping gate dielectric stack featuring a low density of fixed positive charges consists of an O3-based Al2O3 tunneling layer and an O3-based HfO2 blocking layer, both deposited via atomic layer deposition. For HEMT with a 15 nm AlGaN barrier layer, a threshold voltage of 2.57 V and an on-resistance of 8.50 Ω × mm are achieved. For positive bias temperature instability (PBTI) testing, the electric field provided by the 15 nm AlGaN layer serves as a barrier to channel carriers, significantly enhancing the PBTI test stability. The optimized gate dielectric stack enables the fabrication of the non-recessed normally off metal–insulator–semiconductor-HEMT with enhanced threshold voltage (Vth) stability.

(Invited) Tackling Leakage, Drift, and Variation in Printed Carbon Nanotube-Based Electronic Biosensors

Semiconducting carbon nanotubes (CNTs) have been pursued for use in electronic biosensors for decades. Their all-surface molecular structure, sizeable semiconducting bandgap, and solution-phase compatibility make them highly sensitive and versatile options for transducing target bioelectrical signals. However, amid the thousands of reports on CNT-based electronic biosensors, very little attention has been given to identifying (let alone addressing) the impact of leakage current, signal drift, and device-to-device variation. This talk will present recent results focused on tackling these issues with specific emphasis on printed CNT-based biosensors. For instance, a variety of passivation strategies were studied to determine the role of leakage current for CNT transistor-based biosensors (i.e., bioFETs or ion-sensitive FETs), revealing that a bilayer epoxy/high-k dielectric stack was most effective at minimizing unwanted leakage current. The influence of signal drift will also be demonstrated, likely playing a significant role in many previous reports of CNT-based biosensors characterized by sequential concentration spikes. Finally, strategies for addressing device-to-device variation in these biosensors will be discussed, including the motivation for a printed thin-film device rather than a single-CNT configuration. Two things seem certain about this field: 1) the promise of CNT-based biosensors continues to suggest they are worth ongoing pursuit, and 2) there is much work remaining towards achieving a reproducible, reliable electronic biosensing technology from CNTs.

Engineering High-K Switching Devices for in-Memory Computing

Selecting and processing of appropriate stack materials for HfO2-based RRAM devices significantly influences the distribution of defects and oxygen vacancies (Vo) within the switching layer, thereby playing an important role in their switching behavior (1). Controlling this distribution to have more oxygen vacancies near the top electrode (TE) while reducing them near the bottom electrode (BE) results in reduced switching power and enhanced multilevel cell characteristics (MLC) of RRAM devices (2) and that makes them as promising options for in-memory computing. Since RRAM devices fabricated as metal-insulator-metal stack, exploring the impact of each layer remains an active area of research.In this work, we compared different devices by varying the materials of each layer. The first comparison is by varying the oxide layer with same TE (Ru) and BE (TiN) by (i) using stoichiometric HfO2 and (ii) employing HfO2 treated with hydrogen plasma at the midpoint. The device treated with hydrogen plasma consumed nanowatts power compared to the stoichiometric device that consumed hundreds of microwatts to be switched. The introduction of hydrogen plasma treatment at the midpoint of the HfO2layer redirects more Vo towards the TE, explaining the reduction in the switching power (1). While applying pulse SET operation, the hydrogen plasma-treated device exhibited excellent conductance quantization, whereas the stoichiometric device quickly saturated and remaining stuck in a low-resistance state (LRS) due to a lack of Vo (3). Introducing a bilayer Al2O3/HfO2 dielectric significantly decreased switching power consumption to a few microwatts range compared to the stoichiometric device. This reduction is attributed to the rapid formation of Vo within the Al2O3 layer, subsequently stimulating Vo formation within the HfO2layer (4). However, the hydrogen plasma-treated device still maintains the lowest power consumption.Further investigation involved in changing the TE material, Ru and TiN to understand the impact of the TE, given its working function and interface barriers significantly affect the distribution of Vonear the TE. The device using Ru as the TE switched with a 3nA compliance current (1). Introducing nitrogen plasma treatment to the bottom electrode of the TiN device improved its switching behavior due to the reduction Vo near the BE because of formation of the Hf-N bond and led to increase the Vo near the TE (5). This enhancement was marked by a reduction in switching power to picowatts and stabilization of the conductive filament within the oxide. This device demonstrated improved conductance quantization.REFERENCES Patel, Y.; Misra, D.; Triyoso, D.; Clark, R.; Tapily, K.; Consiglio, S.; Wajda, C.; and Leusink, G., "RRAM devices with plasma treated hfo2 with Ru as top electrode for in-memory computing hardware," ECS Transactions, 104(3), p. 35, 2021, DOI: 10.1149/10403.0035ecst.Wong, H.-S. P.; Lee, H. Y.; Yu, Sh.; Chen,Y.; Wu, Y.; Chen, P. Ch.; Lee, B.; Chen, F.T.; Tsai, M. G., "Metal–Oxide RRAM," Proceedings of the IEEE, 2012, DOI: 10.1109/JPROC.2012.2190369.Zeinati, A., Misra, D., Triyoso, D.H., Clark, R.D., Tapily, K., Consiglio, S., Wajda, C.S., Leusink, G.J. "Process Optimization to Reduce Power in hfo2-Based RRAM Devices for in-Memory Computing," ECS Meeting s, vol. MA2022-02, 806 (2022). Doi: 10.1149/MA2022-0215806mtgabsMisra, D.; Zhao, P.; Triyoso, D.; Clark, R.; Tapily, K.; Consiglio, S.; Wajda, C.; Leusink, G., "Dielectrics and Metal Stack Engineering for Multilevel Resistive Random-Access Memory," ECS Journal of Solid-State Science and Technology, 9, 05300, 2020. DOI: 10.1149/2162-8777/ab9dc5.Wang, M.-H.; Chang, T.-Ch.; Shih, Ch.-Ch., "Performance improvement after nitridation treatment in hfo2-based resistance random-access memory," Applied Physics Express, 2018. DOI: 10.7567/APEX.11.084101.

DM-PA-CNTFET Biosensor for Breast Cancer Detection: Analytical Model

In this paper, an analytical model for a novel design dielectric modulated plasma-assisted carbon nanotube field-effect transistor (DM-PA-CNTFET) biosensor is proposed for breast cancer detection. This work is based on a PA-CNTFET in which CNT is used as a channel of FET, and various other device engineering techniques such as dual metal gate-all-around structure and dielectric stack of SiO2 and HfO2 have been used. A comparative analysis of DS-GAAE-CNTFET was performed using a silicon gate all-around FET (Silicon-GAA-FET)-based biosensor. Early detection of breast cancer is made possible by immobilizing MDA-MB-231 and HS578t into the dual-sided nanocavity, which alters the electrical properties of the proposed CNTFET-based biosensor. The DS-GAAE-CNTFET sensor demonstrates a drain ON current sensitivity of 236.9 nA and a threshold voltage sensitivity of 285.58 mV for HS578t cancer cells. Malignant MDA-MB-231 breast cells exhibit a higher drain ON current sensitivity of 343.35 nA and a corresponding threshold voltage sensitivity of 293.23 mV. The exceptional sensitivity and structural resilience of the DS-GAAE-CNTFET biosensor establish it as a promising candidate for early breast cancer detection.

Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing

This study provides a comprehensive investigation on palladium (Pd) gate electrode-based silicon on insulator (SOI) junctionless field-effect transistor (JLFET) for hydrogen gas (H2) sensing (Pd–SOI-JLFET). The device has a gate dielectric stack consisting of silicon dioxide (SiO2) and hafnium dioxide (HfO2). An extensive analysis was conducted to detect and identify the presence of hydrogen gas by examining several electrical characteristics such as drain current (IDS), transconductance (gm), output conductance (gd), energy band diagram (E), gate-to-source capacitance (CGS), and surface potential (Φs). Furthermore, a comprehensive investigation was conducted to examine the impact of the presence of H2 gas and variations in temperature on important parameters associated with the short channel effects (SCEs) including off-state current (IOFF), on-state current (ION), subthreshold swing (SS) and threshold voltage (Vth). In addition, the sensitivity analysis of the off-state current (IOFF) by considering process variation effect has been done. Sensitivity is also calculated at various temperatures for the detection of hydrogen gas molecule. At the temperature of 300K, the sensitivity values were obtained as 1.50083, 3.21754, 27.71483, 152.39617 and 2052.8 for pressure values 10−14 Torr, 10−13 Torr, 10−12 Torr, 10−11 Torr and 10−10 Torr, respectively. This analysis provides a thorough examination of the performance and efficacy of the Pd–SOI-JLFET hydrogen gas sensor highlighting its potential for a wide range of hydrogen sensing applications.

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56 × 10−5 A μm−1, which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635 × 10−12 A/μm. The simulation of the device is carried out with optimization of the doping to investigate and improve the device’s performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

Towards sustainable, direct printed, organic transistors with biocompatible copolymer gate dielectrics

AbstractWe have investigated the potential of three dielectric materials to meet the future demands of green dielectrics: Polycaprolactone (PCL) thermoplastic, polyvinyl alcohol (PVA)‐carrageenan (CAR) crosslinked biopolymer, and boron nitride nanotubes (BNNTs) as a nano additive in PVA. Metal–insulator–metal (MIM) capacitors and organic thin film transistors (OTFT) were built with bilayer dielectric stacks of PVA‐CAR, PVA‐PCL, and PVA‐BNNT materials to examine their electrical properties. The PVA‐CAR layer uses a cyclic freeze thaw process to crosslink PVA and CAR for superior mechanical and electrical properties to either material alone. The PVA‐CAR MIM capacitors showed a dielectric constant of 23, which was found to be consistent with the extracted OTFT gate dielectric characteristics. Of the OTFT devices tested, PVA‐CAR OTFT showed highest device currents at low applied biases and produced an ON/OFF ratio of 104–105, both values were highest amongst the tested gate dielectrics. This material is therefore extremely promising for green electronics. The PVA‐PCL OTFT had very low leakage current and beneficial hydrophilic properties with comparable electrical properties to the commonly used organic material polytetrafluoroethylene. PVA‐BNNT MIM capacitors showed a low dielectric constant of 0.7, and the high resistivity makes this a promising material for shielding or substrates in high frequency applications. All three materials have the potential to fulfil different niches in a sustainable electronics future.

Analysis of TE(z)-Mode Cluster in a Stacked Dielectric Resonator Antenna and Its Bandwidth Diversity Application

Analysis of TE(<i>z</i>)-Mode Cluster in a Stacked Dielectric Resonator Antenna and Its Bandwidth Diversity Application

Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors

Abstract2D semiconductors have emerged as candidates for next‐generation electronics. However, previously reported 2D transistors which typically employ the gate‐first process to fabricate a back‐gate (BG) configuration while neglecting the thorough impact on the dielectric capping layer, are severely constrained in large‐scale manufacturing and compatibility with complementary metal–oxide–semiconductor (CMOS) technology. In this study, dual‐gate (DG) field‐effect transistors have been realized based on wafer‐scale monolayer MoS2 and the gate‐last processing, which avoids the transfer process and utilizes an optimized top‐gate (TG) dielectric stack, rendering it highly compatible with CMOS technology. Subsequently, the physical mechanism of TG dielectric deposition and the corresponding controllable threshold voltage (VTH) shift is investigated. Then the fabricated TG‐devices with a large on/off ratio up to 1.7 × 109, negligible hysteresis (≈14 mV), and favorable stability. Additionally, encapsulated TG structured photodetectors have been demonstrated which exhibit photo responsivity (R) up to 9.39 × 103 A W−1 and detectivity (D*) ≈2.13 × 1013 Jones. The result paves the way for future CMOS‐compatible integration of 2D semiconductors for complex multifunctional IC applications.

Calibration of second harmonic generation technique to probe the field-effect passivation of Si(100) with Al2O3 dielectric layers

Optical second harmonic generation (SHG) can be employed to characterize the passivation quality of semiconducting material interfaces. The interface electric field (EDC) related to the existing charges at and near the interface, including the fixed oxide charges Qox, gives rise to the electric field induced second harmonic phenomenon. In this paper, we calibrate the SHG response for EDC measurement, using Al2O3/SiO2/Si(100) samples with different Qox. To perform this calibration, SHG and capacitance-voltage measurements (to access the electrical field of the samples) were made. The experimental results match well the simulated calibration curve, proving the potential of the SHG as stand-alone characterization technique for dielectric stacks on Si.

Complementary negative capacitance field-effect transistors based on vertically stacked van der Waals heterostructures

Complementary field-effect transistors (CFETs) with a vertically stacked n-FET/p-FET configuration can provide a promising solution to boost area efficiency. However, the substantial power dissipation exhibited by these CFET devices poses a notable challenge to the energy efficiency. By combining a negative-capacitance field-effect transistor (NCFET) and a CFET, the problem of excessive power consumption can be solved. By using a negative-capacitance gate stack, the supply voltage (Vdd) applied to the gate of the CFET is increased, resulting in a reduction in power consumption. Here, we experimentally demonstrate a vertically integrated complementary negative capacitance field-effect transistor (NC-CFET) that combines tungsten diselenide (WSe2) p-NCFET and molybdenum disulfide (MoS2) n-NCFET. With the hexagonal boron nitride/copper indium thiophosphate CuInP2S6 (CIPS) dielectric stack, both n-type and p-type van der Waals (vdW) NCFETs exhibit sub-60 mV/decade switching characteristics. The vdW NC-CFET exhibits a voltage gain of 78.34 and a power consumption of 129.7 pW at a supply voltage of 1 V. These device characteristics demonstrate the great potential of the vdW NC-CFET for high density and low power applications.

Tunable optical absorption in undoped graphene sandwiched between multilayer dielectric stacks with mirror symmetry

We theoretically investigate the optical absorption of an undoped graphene monolayer when put in a one-dimensional multilayer stack. Using the transfer matrix method, we perform numerical simulations and derive explicit analytical formulas for the optical absorption of the graphene monolayer at the center of the dielectric stack and find that the optical absorption uniquely depends on repetition number (r) and the unit layers structure. When sandwiched between unit layers structure composed of three dielectric materials (referred to as the ‘ABC’ structure) with even values of r, the graphene monolayer absorbs 2.3% of visible to near-infrared light. This behavior is the same as if graphene were free-standing, not sandwiched between the dielectric stack. In contrast to that situation, in the ABC structure with odd values of r, also when the graphene monolayer is sandwiched between four materials (the ‘ABCD’ structure) with any values of r, we can obtain optical absorption as large as 50% at particular refractive indices (n) of the constituent dielectric materials. The 50% absorption is, in fact, the maximum optical absorption for any undoped monolayer material in the symmetric dielectric stacks. By varying r and n within the ABC or ABCD structures, we can finely adjust the optical absorption of graphene within the range of 0%–50%, facilitating precise control for various optoelectronic applications.

Improved performance of H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks deposited by electron beam method

H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks were fabricated using an electron beam (EB) evaporation technique. The fixed positive charge in the ZrO2 contact layer depleted the two-dimensional hole gas to achieve normally off operation. Thanks to the leakage suppression of Al2O3 blocking layer, the device exhibited a considerably low gate leakage current of 1.8 × 10−6 A/cm2 at VGS = −5 V. Contributed from the relatively lower estimated interfacial state density (1.45 × 1012 cm−2 eV−1) and uncontaminated ZrO2/Al2O3 gate interface, the maximum mobility was estimated to be 345.8 cm2/V·s at VGS of −2 V, indicating excellent interfacial property of ZrO2/H-diamond. The hole mobility remains an almost constant of about 150 cm2/V·s for −4 V ≤ VGS ≤ −7 V. The maximum drain current density with 6 μm-gate length was −112 mA/mm at VGS of −7 V. These results will provide an approach for fabricating high-performance H-diamond FETs.

The Proposition of a Dual-Sensitivity Laminated Multimetal Dielectric Stacks Detecting Structure Based on the Reflected Goos–Hänchen Effect

The Proposition of a Dual-Sensitivity Laminated Multimetal Dielectric Stacks Detecting Structure Based on the Reflected Goos–Hänchen Effect

Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability

This paper investigates In[Formula: see text]Ga[Formula: see text]As/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO2 as dielectric stack over SiO2 provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.

(Invited) Gallium Nitride for Vertical Power Devices: Improving Morphology and Unintentional Impurities for Better Devices

While GaN has been researched for many years as a material for light emitting diodes, lasers, high electron mobility transistors, and other devices, further improvements to material purity are still needed to realize the full potential of this material for vertical device applications. To achieve high quality, high purity GaN for power devices, our research employs ammonia-assisted molecular beam epitaxy (NH3-MBE) and plasma-assisted molecular beam epitaxy (PA-MBE). Past studies of fast growth rates (more than 1 μm/hr) and ultra-low impurity incorporation revealed that both PAMBE and NH3-MBE can achieve low net doping levels, and NH3-MBE as low as 1x1015 cm-3.1 However, This work also indicated that impurity incorporation increased with increasing growth rate.Recent research efforts have focused on further improvements to morphology and unintentional dopants in NH3-MBE-grown homoepitaxial layers with fast growth rates. By optimizing growth conditions for faster growth rates and using indium as a surfactant, devices with drift layers up to 10 μm thick were grown. These layers exhibited smooth surface morphology as seen in AFM scans with RMS surface roughness as low as 0.21 nm for a 2x2 μm2 scan area.2 Adding the In surfactant also led to reduced incorporation of unintentional Si impurities in UID films as shown by SIMS depth profiles for GaN films grown with and without In. The extremely low impurity levels were further confirmed by CV measurements which indicated that the net doping density in the UID GaN layers decreased from 2x1016 cm-3 to 5x1015 cm-3 with the addition of the In surfactant.2 Based on these UID levels and the theoretical critical electric field of GaN (3 MV/cm), drift layers up to 29.5 μm and 7.4 μm can be depleted with a triangular electric field profile for net donor concentrations of 5x1015 cm-3 and 2x1016 cm-3, respectively. Devices with the same net concentrations with drift regions 3 μm thick can hold voltages of 854 V and 717 V, respectively.Based on the previously described studies of low-impurity GaN at different growth rates, we developed vertical p-n GaN power devices grown by NH3 MBE.3 These p-n diodes contained a 0.25 µm n+ region, 4 µm n- region with 3x1015 cm-3 unintentional carriers, 0.4 µm p+ region and 10nm p++ capping layer to improve the ohmic anode contact. The circular diodes were fabricated with Pd/Pt anode contacts and Ti/Au cathode contacts. Device diameters were between 80 and 100 µm. The devices featured a 15 µm field plate made from Ti/Au contacts on top of an Al2O3/Si3N4 dielectric stack.The diodes exhibited outstanding forward J-V behavior with a low specific on-resistance (Ron,sp) of 0.28 mΩ-cm2 and a minimum ideality factor of 1.36, which are among the best achieved among similar homoepitaxial GaN p-n diodes.3-5 The best diodes also exhibited a breakdown voltage of > 1 kV (equipment limit 1 kV). The reverse-voltage properties indicate that punch-through was achieved with a peak electric field (EC) >2.6 MV/cm, as confirmed by Silvaco simulations (Fig. 7). The combination of >1 kV breakdown voltage and on-resistance of 0.28 mΩ-cm2 represents one of the best performances of the p-n GaN diodes, achieved with a significantly thinner drift layer compared to comparable MOCVD GaN p-n diodes with drift layers more than 8 µm. Work is ongoing to develop NH3-MBE p-n diodes with indium surfactant-assisted drift layer growth which shows promise to further improve the surface morphology, reduce leakage, and enhance breakdown performance of the vertical devices.

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

Horizontally aligned ALD-SnO films grown on SiO2-passivated high-k HfO2 dielectrics for high-mobility and low-power P-channel thin-film transistor

The fabrication of SiO2-passivated HfO2 (HfO2/SiO2) as a high-k dielectric stack for high-mobility, low-power p-channel SnO thin-film transistors (TFTs) is reported herein. To achieve superior TFT performance, a high-k HfO2 film was introduced by replacing the thermally-grown SiO2. However, the atomic layer deposited (ALD)-SnO films grown on the HfO2 substrate exhibited a very rough surface and out-of-plane tilted SnO (001), resulting in a significantly degraded field-effect mobility (μFE) compared with that of SnO TFTs based on an SiO2 gate dielectric. Therefore, 1–10 nm-thick ALD-SiO2 passivation layers were deposited on high-k HfO2 to effectively improve the surface morphology of the ALD SnO. Furthermore, SiO2 passivation enabled the control of the crystallographic orientation of the ALD SnO. Through SiO2 passivation, the horizontally aligned SnO (00l) planes parallel to the substrate demonstrated significantly improved μFE characteristics. The optimized SnO TFTs fabricated with HfO2/SiO2 stacks exhibited excellent carrier transport and low-voltage operation characteristics, with μFE of 2.3 cm2/V·s, subthreshold swing of 0.5 V/dec, on-to-off drain current ratio of 1.4 × 104, and Vth of −1.2 V.

Physics-based analytical model for trap assisted biosensing in dual cavity negative capacitance junctionless accumulation mode FET

The design of a ferroelectric-based biosensor for detecting various biomolecules like proteins and DNA has captivated the interest of researchers in early disease diagnostics and treatment monitoring. Doomed by this interest, an analytical model for trap-assisted biosensing in Dual Cavity Negative Capacitance Junctionless Accumulation Mode FET is proposed for detecting various biomolecules. The biomolecules are treated as traps that tunnel through the biosensor's ferroelectric layer. The analytical model is validated through extensive numerical device simulations. The device incorporates the detection of charged and uncharged biomolecules in terms of dielectric constants and biomolecule concentration. The nano-cavities are created inside the gate dielectric stack to collect biomolecules like proteins and DNA. As the biomolecules are infused as traps in cavity areas, electrical properties of the biosensor, like input characteristics, transconductance, threshold voltage, on-state current, and subthreshold swing change. The sensitivity obtained for the proposed biosensor is compared with the existing biosensor and found that it is best suited for susceptible biosensing applications.

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.