Stack Usage Research Articles

Deploying the ATLAS Metadata Interface (AMI) stack in a Docker Compose or Kubernetes environment

ATLAS Metadata Interface (AMI) is a generic ecosystem for metadata aggregation, transformation and cataloging. This paper describes how a renewed architecture and integration with modern technologies ease the usage and deployment of a complete AMI stack. It describes how to deploy AMI in a Docker Compose or Kubernetes environment, with a particular emphasis on the registration of existing databases, the addition of more metadata sources, and the generation of high level Web search interfaces using dedicated wizards.

Model Predictive Control Strategies for Turbine Electrified Energy Management

Abstract The increasing electrification of aircraft propulsion systems is leading to new control architectures being developed to address integration between electric machines and gas-based turbine engines. For hybrid-electric propulsion systems, current conceptual architectures often couple electric machines with the shafts of gas turbine engines and introduce energy storage. Leveraging the electrical power system of hybridized engines, Turbine Electrified Energy Management (TEEM) is a recent control approach that improves transient operability in an effort to enable more efficient and lighter weight turbomachinery. This study seeks to expand TEEM's application beyond traditional proportional-integral (PI) control by presenting linear model predictive control (MPC) schemes to execute the TEEM concept. Through constraint selection and cost function design, transient operability goals for TEEM are considered with no external logic or saturation. Unique to the designs are the use of a washout filter, which simplifies transient detection and motor activation logic. The proposed architectures are implemented with both centralized MPC and distributed MPC approaches, and comparisons are drawn to a benchmark PI controller simulated on a nonlinear turbofan engine model at one ground condition and one cruise condition. Performance is evaluated using compressor maps, stall margin performance, and two novel metrics: transient stack usage and transient excursion integral. Results reveal the linear MPC scheme performs comparably to the baseline controller and can be implemented in at least two distinct configurations with potential for further modifications, thus establishing the groundwork for future investigations.

Minimizing Stack Memory for Partitioned Mixed-criticality Scheduling on Multiprocessor Platforms

A Mixed-Criticality System (MCS) features the integration of multiple subsystems that are subject to different levels of safety certification on a shared hardware platform. In cost-sensitive application domains such as automotive E/E systems, it is important to reduce application memory footprint, since such a reduction may enable the adoption of a cheaper microprocessor in the family. Preemption Threshold Scheduling (PTS) is a well-known technique for reducing system stack usage. We consider partitioned multiprocessor scheduling, with Preemption Threshold Adaptive Mixed-Criticality (PT-AMC) as the task scheduling algorithm on each processor and address the optimization problem of finding a feasible task-to-processor mapping with minimum total system stack usage on a resource-constrained multi-processor. We present the Extended Maximal Preemption Threshold Assignment Algorithm (EMPTAA), with dual purposes of improving the taskset’s schedulability if it is not already schedulable, and minimizing system stack usage of the schedulable taskset. We present efficient heuristic algorithms for finding sub-optimal yet high-quality solutions, including Maximum Utilization Difference based Partitioning (MUDP) and MUDP with Backtrack Mapping (MUDP-BM), as well as a Branch-and-Bound (BnB) algorithm for finding the optimal solution. Performance evaluation with synthetic task sets demonstrates the effectiveness and efficiency of the proposed algorithms.

Tuning the top-seeded melt growth of REBCO single-domain superconducting bulks by a pyramid-like buffer stack

In this contribution, the usage of a pyramid-like buffer stack for optimization of the top-seeded melt growth process of GdBCO (GdBa 2 Cu 3 O 7-δ ) single-domain superconductors is demonstrated. The process was optimized by the addition of SmBCO into GdBCO/Ag into the buffer precursor powder, which effectively increased the peritectic temperature of the final mixed powder in the pyramid-like buffer stack. As such, this approach can be also used for other REBCO systems by selecting rare earth with a higher peritectic temperature and adding it to the buffer pellets. The thermal behavior of the powders was studied by STA. This enables fast and effective crystal growth through the buffer stack and the formation of large effective seeds. This approach also allows for reliable and precise tuning of growth angle and together with effective seed size facilitates tuning of a - b to c sector ratio. The phase composition of precursors and prepared bulks were studied by XRD. The microstructure was also studied by SEM and OM in detail. Subsequently, levitation force and trapped field were measured. Results confirmed that the addition of at least a single buffer pellet improved the melt growth process significantly by acting as a large effective seed. Superconducting properties of the samples grown by pyramid-like buffer stack are superior in comparison to reference TSMG samples.

Schedulability analysis and stack size minimization for adaptive mixed criticality scheduling with semi-Clairvoyance and preemption thresholds

In cost-sensitive Mixed-Criticality Systems (MCS) such as automotive Electrical/Electronic (E/E) systems, it is important to reduce application memory footprint, since such a reduction may enable significant cost savings due to adoption of cheaper processor models. Preemption Threshold Scheduling (PTS) is an effective technique for controlling the degree of preemption and reducing system stack usage of a multitasking system under priority-based scheduling. In this paper, we present a schedulability test to enable integration of Preemption Threshold Scheduling (PTS) and Adaptive Mixed Criticality (AMC) scheduling with Semi-Clairvoyance, which can be used by high-level optimization algorithms with different possible optimization objectives, including improving schedulability and reducing system stack usage of an MCS. The experimental results indicate that our approach results in significant benefits in terms of improving schedulability and reducing system stack usage compared to state-of-the-art.

Multi-moduli NTTs for Saber on Cortex-M3 and Cortex-M4

The U.S. National Institute of Standards and Technology (NIST) has designated ARM microcontrollers as an important benchmarking platform for its Post-Quantum Cryptography standardization process (NISTPQC). In view of this, we explore the design space of the NISTPQC finalist Saber on the Cortex-M4 and its close relation, the Cortex-M3. In the process, we investigate various optimization strategies and memory-time tradeoffs for number-theoretic transforms (NTTs).Recent work by [Chung et al., TCHES 2021 (2)] has shown that NTT multiplication is superior compared to Toom–Cook multiplication for unprotected Saber implementations on the Cortex-M4 in terms of speed. However, it remains unclear if NTT multiplication can outperform Toom–Cook in masked implementations of Saber. Additionally, it is an open question if Saber with NTTs can outperform Toom–Cook in terms of stack usage. We answer both questions in the affirmative. Additionally, we present a Cortex-M3 implementation of Saber using NTTs outperforming an existing Toom–Cook implementation. Our stack-optimized unprotected M4 implementation uses around the same amount of stack as the most stack-optimized Toom–Cook implementation while being 33%-41% faster. Our speed-optimized masked M4 implementation is 16% faster than the fastest masked implementation using Toom–Cook. For the Cortex-M3, we outperform existing implementations by 29%-35% in speed. We conclude that for both stack- and speed-optimization purposes, one should base polynomial multiplications in Saber on the NTT rather than Toom–Cook for the Cortex-M4 and Cortex-M3. In particular, in many cases, multi-moduli NTTs perform best.

Cortex-M4 optimizations for {R,M} LWE schemes

This paper proposes various optimizations for lattice-based key encapsulation mechanisms (KEM) using the Number Theoretic Transform (NTT) on the popular ARM Cortex-M4 microcontroller. Improvements come in the form of a faster code using more efficient modular reductions, optimized small-degree polynomial multiplications, and more aggressive layer merging in the NTT, but also in the form of reduced stack usage. We test our optimizations in software implementations of Kyber and NewHope, both round 2 candidates in the NIST post-quantum project, and also NewHope-Compact, a recently proposed variant of NewHope with smaller parameters. Our software is the first implementation of NewHope-Compact on the Cortex-M4 and shows speed improvements over previous high-speed implementations of Kyber and NewHope. Moreover, it gives a common framework to compare those schemes with the same level of optimization. Our results show that NewHope- Compact is the fastest scheme, followed by Kyber, and finally NewHope, which seems to suffer from its large modulus and error distribution for small dimensions.

Optimum Load Sharing And Improving Stability In Distribution Network (LT)

This assignment paintings gives outline and reenactment of looking at, fault discovery of transformer, 3 level stack usage and misfortune assessment. undertaking indictors of a scattering transformer like load modern-day, voltage, transformer oil and incorporating temperatures and moistness. They need to take a gander at it consistently by using utilising this undertaking it is able to restrict working endeavors and enhance exactness, solidness, effectiveness in this mission, sensors are utilized to discover the primary parameters of equipment, for instance, voltage, present day(over voltage, underneath voltage, over contemporary) this detected data is despatched to microcontroller and this controller tests parameter limits which moreover ship to the EB control section[19],[20],[21]

A hybrid approach to testing for nonfunctional faults in embedded systems using genetic algorithms

SummaryEmbedded systems are challenging to program correctly, because they use an interrupt‐driven programming paradigm and run in resource‐constrained environments. This leads to various classes of nonfunctional faults that can be detected only by customized verification techniques. These nonfunctional faults are specifically related to usage of resources such as time and memory. For example, the presence of interrupts can induce delays in interrupt servicing and in system execution time. Such delays can occur when multiple interrupt service routines and interrupts of different priorities compete for resources on a given CPU. As another example, stack overflows are caused when the combination of active methods and interrupt invocations on the stack grows too large, and these can lead to data loss and other significant device failures. To detect these types of nonfunctional faults, developers need to estimate worst‐case resource usage. Most existing approaches for calculating such estimates are based on static analysis; however, these have a tendency to overapproximate the resources needed. Dynamic techniques such as random testing, in contrast, often underapproximate resource usage. In this article, we present SimEspresso, a framework that uses a combination of static analysis and a test case generation algorithm to estimate worst‐case resource usage. There are three different worst‐case resource usage scenarios that we consider: (1) worst‐case execution times, (2) worst‐case interrupt latencies, and (3) worst‐case stack usage. SimEspresso first uses static analysis to identify program paths and interrupt interleavings that potentially lead to worst‐case scenarios. It then uses a genetic algorithm to generate test cases that guide program execution down these paths, using these particular interrupt interleavings. We performed an empirical study to evaluate the effectiveness of SimEspresso; our results show that SimEspresso is more effective than static analysis approaches and improves significantly over the state of the art dynamic technique, random test case generation. We also find that when we use only the genetic algorithm, omitting the static analysis, SimEspresso performs almost as effectively, but takes significantly longer to complete its task.

Standard Lattice-Based Key Encapsulation on Embedded Devices

Lattice-based cryptography is one of the most promising candidates being considered to replace current public-key systems in the era of quantum computing. In 2016, Bos et al. proposed the key exchange scheme FrodoCCS, that is also a submission to the NIST post-quantum standardization process, modified as a key encapsulation mechanism (FrodoKEM). The security of the scheme is based on standard lattices and the learning with errors problem. Due to the large parameters, standard latticebased schemes have long been considered impractical on embedded devices. The FrodoKEM proposal actually comes with parameters that bring standard lattice-based cryptography within reach of being feasible on constrained devices. In this work, we take the final step of efficiently implementing the scheme on a low-cost FPGA and microcontroller devices and thus making conservative post-quantum cryptography practical on small devices. Our FPGA implementation of the decapsulation (the computationally most expensive operation) needs 7,220 look-up tables (LUTs), 3,549 flip-flops (FFs), a single DSP, and only 16 block RAM modules. The maximum clock frequency is 162 MHz and it takes 20.7 ms for the execution of the decapsulation. Our microcontroller implementation has a 66% reduced peak stack usage in comparison to the reference implementation and needs 266 ms for key pair generation, 284 ms for encapsulation, and 286 ms for decapsulation. Our results contribute to the practical evaluation of a post-quantum standardization candidate.

Design optimization for AUTOSAR models with preemption thresholds and mixed-criticality scheduling

Preemption Threshold Scheduling (PTS) is an effective technique for reducing stack memory usage by selectively disabling preemption between pairs of tasks.We consider the AUTOSAR standard in automotive embedded software development, where each task consists of multiple runnables that are scheduled with static priority and preemption threshold.We address the problems of design synthesis from an AUTOSAR model to minimize stack usage for mixed-criticality systems with preemption threshold scheduling, and present algorithms for schedulability analysis and stack usage minimization.Experimental results demonstrate that our approach can significantly reduce the system stack usage. Safety-critical embedded systems are often subject to multiple certification requirements from different certification authorities, giving rise to the concept of Mixed-Criticality Systems. Preemption Threshold Scheduling (PTS) is an effective technique for reducing stack memory usage by selectively disabling preemption between pairs of tasks. In this paper, we consider the AUTOSAR standard in automotive embedded software development, where each task consists of multiple runnables that are scheduled with static priority and preemption threshold. We address the problems of design synthesis from an AUTOSAR model to minimize stack usage for mixed-criticality systems with preemption threshold scheduling, and present algorithms for schedulability analysis and system stack usage minimization. Experimental results demonstrate that our approach can significantly reduce the system stack usage.

Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling

Multicore processors are increasingly adopted in resource-constrained real-time embedded applications. In the development of such applications, efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and to reduce system stack usage. In this paper, we consider partitioned multi-processor scheduling on a multicore processor with either Fixed-Priority or Earliest Deadline First scheduling algorithms with PTS and address the design optimization problem of mapping tasks to processor cores and assignment of task priorities and preemption thresholds with the optimization objective of minimizing system stack usage. We present both optimal solution techniques based on Mixed Integer Linear Programming and efficient heuristic algorithms that can achieve high-quality results. We perform extensive performance evaluations using both synthetic tasksets and industrial case studies.

Underapproximation of procedure summaries for integer programs

We show how to underapproximate the procedure summaries of recursive programs over the integers using off-the-shelf analyzers for non-recursive programs. The novelty of our approach is that the non-recursive program we compute may capture unboundedly many behaviors of the original recursive program for which stack usage cannot be bounded. Moreover, we identify a class of recursive programs on which our method terminates and returns the precise summary relations without underapproximation. Doing so, we generalize a similar result for non-recursive programs to the recursive case. Finally, we present experimental results of an implementation of our method applied on a number of examples.

Combined WCET analysis of bitcode and machine code using control-flow relation graphs

Static program analyses like stack usage analysis and worst-case execution time (WCET) analysis depend on the actual machine code generated by the compiler for the target system. As the analysis of binary code is costly, hard to diagnose and platform dependent, it is preferable to carry out parts of these analyses on a higher-level program representation. To this end, the higher-level code and the machine code need to be related, a difficult task due to the complexity of modern optimizing compilers. In this article, we present a novel representation called control-flow relation graphs, which provide an accurate model of the control-flow relation between machine code and the compiler's intermediate representation. In order to facilitate the integration of our approach in existing compiler frameworks, we develop a construction algorithm that builds the control-flow relation graph from partial mappings provided by the compiler. The WCET calculation method for control-flow relation graphs processes flow information from both the intermediate representation and machine code. Furthermore, we demonstrate the transformation of flow information from the IR to the machine code level, in order to use existing industrial-strength WCET analysis tools operating on machine code. We implemented the construction algorithm within the LLVM compiler framework, along with an implementation of the combined WCET calculation method. The evaluation demonstrates that the approach is able to relate bitcode (LLVM's intermediate representation) and machine code in a precise way, with a WCET increase of at most 2% when using flow facts on the bitcode level, compared to equivalent ones on the machine-code level. As the methods presented in this article provide a cost-effective way to reuse platform independent flow information, they have the potential to simplify WCET analysis, and popularize its use in the development process of real-time systems.

무작위수생성을 위한 부 페레즈 함수

We study sub-Peres functions that are defined recursively as Peres function for random number generation. Instead of using two parameter functions as in Peres function, the sub-Peres functions uses only one parameter function. Naturally, these functions produce less random bits, hence are not asymptotically optimal. However, the sub-Peres functions runs in linear time, i.e., in O(n) time rather than O(n logn) as in Peres`s case. Moreover, the implementation is even simpler than Peres function not only because they use only one parameter function but because they are tail recursive, hence run in a simple iterative manner rather than by a recursion, eliminating the usage of stack and thus further reducing the memory requirement of Peres`s method. And yet, the output rate of the sub-Peres function is more than twice as much as that of von Neumann`s method which is widely known linear-time method. So, these methods can be used, instead of von Neumann`s method, in an environment with limited computational resources like mobile devices. We report the analyses of the sub-Peres functions regarding their running time and the exact output rates in comparison with Peres function and other known methods for random number generation. Also, we discuss how these sub-Peres function can be implemented.

SenSmart: Adaptive Stack Management for Multitasking Sensor Networks

The networked application environment has motivated the development of multitasking operating systems for sensor networks and other low-power electronic devices, but their multitasking capability is severely limited because traditional stack management techniques perform poorly on small-memory systems without virtual memory support. In this paper, we show that combining binary translation and a new kernel runtime can lead to efficient OS designs on resource constrained platforms. We introduce SenSmart, a multitasking OS for sensor networks, and present new OS design techniques for supporting preemptive multitask scheduling, memory isolation, and adaptive stack management. Our solution provides memory isolation and automatic stack relocation on usual sensornet platforms. The adaptive stack management frees programmers from the burden of estimating tasks' stack usage, yet it enables SenSmart to schedule and run more tasks than other multitasking OSes for sensor networks. We have implemented SenSmart on MICA2/MICAz motes. Evaluation shows that SenSmart has a significantly better capability in managing concurrent tasks than other sensornet operating systems.

A Robust and Space-Efficient Stack Management Method for Wireless Sensor Network OS with Scarce Hardware Resources

Due to such requirements as low power consumption and low cost, sensor nodes commonly do not include advanced H/W features. The absence of the features such as the memory management unit enforces several tasks to share a memory address domain on a small data memory space (1 ~16 KB). It exposes each task to the stack overflow causing the corruption of other memory areas. In this paper, we propose a robust and efficient stack memory management method (RESM) that dynamically assigns and releases a preestimated amount of stack memory to each function call at runtime. RESM maintains the stack memory usage with the similar amount of the stack usage that the system actually requires, and the stack memory area of each task is individually protected from corruption by the stack overflow. RESM can also anticipate a saturated condition in data memory at runtime. When the memory state is unsafe from the saturated condition, it conditionally allows function calls to operate tasks without any memory fault by using the proposed function call deferring algorithm. From the analytical and experiment results, it is proven that the performance of RESM outperforms the other mechanisms and RESM can provide more robust stack operation environment.

Efficient and Systematic Solution of Real and Complex Eigenvalue Problems Employing Simplex Chain Vertices Searching Procedure

This paper presents a novel method that is very efficient in solving multidimensional real and complex eigenvalue problems, commonly employed in electromagnetic analysis, which can be transformed into a nonlinear equation. The concept is realized as root tracing process of a real or complex function of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> variables in the constrained space. We assume that the roots of the continuous function of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> variables lie on the continuous ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -1) -dimensional hyperplane. The method uses regular <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> and ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -1)-Simplexes, at which vertices the considered function changes its sign. Based on ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -1)-Simplex, the function is evaluated at two new points that are vertices of new regular <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -Simplexes for which ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -1)-Simplex is one of its ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -1)-faces. The algorithm, with the usage of stack, runs in an iterative mode tracing the roots inside the volume of the considered simplexes. As a result, the algorithm creates a chain of simplexes in the constrained region. The proposed algorithm is optimal in the sense of the number of function evaluations. The numerical results, real and complex dispersion characteristics of chosen microwave guides, have proven the versatility and efficiency of the proposed algorithm.

Study on Approach of Determining Size of µC/OS-II Task Stack

When μC/OS-II is taken as the operating system of an embedded system, the stack size of every task is needed to be assigned, but it is difficult to determine the stack size of µC/OS-II task with existing methods. In this paper, an approach of determining stack size of µC/OS-II task was presented. In order to clarify the memory space size which is needed by single element in a µC/OS-II task stack, the contents of µC/OS-II task stack were analyzed. Secondly, some tree structures were defined, which can describe the extreme usage of task stack. Lastly, two formulas used to determine size of task stack were presented. As long as the source codes of µC/OS-II operating system and its task are obtained, the stack size of the task can be computed accurately with the approach presented by this paper. The result acquired with the approach is the maximum size of task stack, it can meet the needs of µC/OS-II task for stack space at any cases.

SLAW

This poster introduces SLAW, a Scalable Locality-aware Adaptive Work-stealing scheduler. The SLAW features an adaptive task scheduling algorithm combined with a locality-aware scheduling framework. Past work has demonstrated the pros and cons of using fixed scheduling policies, such as work-first and help-first , in different cases without a clear winner. Prior work also assumes the availability and successful execution of a serial version of the parallel program. This assumption can limit the expressiveness of dynamic task parallel languages. The SLAW scheduler supports both work-first and help-first policies simultaneously. It does so by using an adaptive approach that selects a scheduling policy on a per-task basis at runtime. The SLAW scheduler also establishes bounds on the stack usage and the heap space needed to store tasks. The experimental results for the benchmarks studied show that SLAW's adaptive scheduler achieves 0.98x - 9.2$x speedup over the help-first scheduler and 0.97x - 4.5x speedup over the work-first scheduler for 64-thread executions, thereby establishing the robustness of using an adaptive approach instead of a fixed policy. In contrast, the help-first policy is 9.2x slower than work-first in the worst case for a fixed help-first policy, and the work-first policy is 3.7x slower than help-first in the worst case for a fixed work-first policy. Further, for large irregular recursive parallel computations, the adaptive scheduler runs with bounded stack usage and achieves performance (and supports data sizes) that cannot be delivered by the use of any single fixed policy. The SLAW scheduler is designed for programming models where locality hints are provided to the runtime by the programmer or compiler, and achieves locality-awareness by grouping workers into places . Locality awareness can lead to improved performance by increasing temporal data reuse within a worker and among workers in the same place. Our experimental results show that locality-aware scheduling can achieve up to 2.6x speedup over locality-oblivious scheduling, for the benchmarks studied.