Square Root Circuit Research Articles

Driving magnetic oscillation by electric flip in Permalloy/BaTiO3 composite

In this work, the Permalloy/BaTiO3 composite with granule/matrix structure is designed. The theoretical calculation reveals coupling between electric polarization and magnetic anisotropy. As electric polarization is downward and upward in BaTiO3 matrix, the magnetizing orientation tends to be parallel and perpendicular in Permalloy granule respectively. The Landau-Lifshitz-Gilberts model further predicts magnetic oscillation driven by electric flip. Explicitly, as electric polarization flips with low frequency in BaTiO3 matrix, the magnetic moment oscillates with high frequency in Permalloy granule. It results from the anisotropy field altered periodically by polarization flip. Based on the magnetic tunneling model, the moment oscillation can output periodical voltage signal. With the Square-Root circuit, the oscillating amplitude of output voltage becomes stable. Through 4-level connection of this design, the 1.0 MHz input can drive 3.5 GHz output. This work gives a novel strategy for spin torque nano-oscillator. Compared to the spin-transfer torque method, this avenue could avoid the heat influence of current.

FEN1-assisted DNA logic amplifier circuit for fast and compact DNA computing.

This work developed DNA amplifier logic gates (AND-OR, OR-AND, FAN-IN, FAN-OUT, and 4-bit square-root circuits) using a flap endonuclease 1 (FEN1)-catalyzed signal amplification reaction, for the fastest and compact DNA computing. Moreover, the logic circuit can use input strands with concentrations of less than 1 nM, which is more than 100 times lower than the input concentration of other DNA logic circuits, providing a promising methodology for constructing fast and compact DNA computations.

Modified restoring array-based power efficient approximate square root circuit and its application

In this paper, the authors present an investigation into the benefits of approximate computing in energy-efficient error-resilient applications. It proposes an approximate square root (SQR) circuit based on the modified restoring array square root (MRAS) architecture. The MRAS design incorporates strategic elimination, optimization, and simplification of restoring subtractor cells (SC) within a conventional restoring array SQR circuit. As a result, the proposed MRAS circuit efficiently computes the square root of a 2n-bit unsigned integer, offering a 27 percent reduction in area, 13 percent faster computation, and 50 percent lower power consumption compared to the exact SQR design. To introduce approximation, configurable SCs are integrated into the MRAS circuit, enabling dual operation modes for both accuracy and approximation. This feature allows the proposed approximate modified restoring array SQR (AMRAS) design to cater to both error-resilient and error-sensitive applications. The evaluation involves a thorough analysis of accuracy and design metrics for 16-bit unsigned exact, state-of-the-art, and proposed square rooters. The designs are implemented on Artix7 FPGA using Verilog-HDL and simulated in the Xilinx Vivado simulator. The results demonstrate that the proposed AMRAS achieves a good trade-off between accuracy and hardware, presenting an impressive 80 percent reduction in power consumption and a 36 percent faster computation. Additionally, the paper showcases the practical application of the proposed AMRAS square rooters in the Sobel edge detection for image processing.

Non-complementary strand commutation as a fundamental alternative for information processing by DNA and gene regulation.

The discovery of the DNA double helix has revolutionized our understanding of data processing in living systems, with the complementarity of the two DNA strands providing a reliable mechanism for the storage of hereditary information. Here I reveal the 'strand commutation' phenomenon-a fundamentally different mechanism of information storage and processing by DNA/RNA based on the reversible low-affinity interactions of essentially non-complementary nucleic acids. I demonstrate this mechanism by constructing a memory circuit, a 5-min square-root circuit for 4-bit inputs comprising only nine processing ssDNAs, simulating a 572-input AND gate (surpassing the bitness of current electronic computers), and elementary algebra systems with continuously changing variables. Most importantly, I show potential pathways of gene regulation with strands of maximum non-complementarity to the gene sequence that may be key to the reduction of off-target therapeutic effects. This Article uncovers the information-processing power of the low-affinity interactions that may underlie major processes in an organism-from short-term memory to cancer, ageing and evolution.

Simple Current-Mode Squaring and Square-Rooting Circuits: Applications of MO-CCCCTA

This work provides new designs of simple current-mode squaring and square-rooting circuits using multiple-output current controlled current conveyor transconductance amplifier (MO-CCCCTA) as an active building block. Since the proposed circuits need no other external components, they are capable of high-frequency operation and well fitted for IC fabrication. Furthermore, they are insensitive to ambient temperature and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA. Additionally, the effects of MO-CCCCTA non-idealities on the designed circuits have also been investigated and discussed. Simulation results generated through PSPICE software using TSMC 0.18 µm CMOS process parameters have been presented to justify the theoretical analysis. The static power consumption, bandwidth, and maximum linearity error in dc transfer characteristic measurement for the square-rooting circuit are found to be 0.17 mW, 445.63 MHz and 1.12 %, while for the squaring circuit they are 0.326 mW, 61.15 MHz and 2.38 %, respectively. The application of the reported circuits as a 2-input vector summation circuit has also been included to strengthen the design ideas.
 HIGHLIGHTS
 
 Simple structures of fully integrable current-mode squarers and square-rooters with low component count and lower power dissipation
 The circuits are insensitive to temperature drift and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA
 Bandwidth, static power dissipation, linearity error of square-rooter are 445.63 MHz, 0.17 mW & ≤ 1.12 %; and for the squarer 61.15 MHz, 0.326 mW & 2.38 %, respectively
 
 GRAPHICAL ABSTRACT

A Low-Cost High Radix Floating-Point Square-Root Circuit

In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation

In this paper, an adaptive approximation approach is proposed for the design of a divider and a square root (SQR) circuit. In this design, the division/SQR is computed by using a reduced-width divider/SQR circuit and a shifter by adaptively pruning some insignificant input bits. Specifically, for a $2n/n$2n/n division, $2k$2k and $k$k ($k<n$k<n) consecutive bits are selected starting from the most significant ‘1’ in the dividend and divisor, respectively. At the same time, redundant least significant bits (LSBs) are truncated or if the number of remaining bits after pruning is smaller than the number of bits to be kept, ‘0's are appended to the LSBs of the inputs. To avoid overflow, a $2(k+1)/(k+1)$2(k+1)/(k+1) divider is used to compute the $2k/k$2k/k division. Finally, an error correction circuit is proposed to recover the error caused by the shifter using OR gates. For a $2n$2n-bit approximate SQR circuit, similar pruning schemes are used to obtain a $2k$2k-bit radicand. A $2k$2k-bit SQR circuit and a shifter are then utilized to compute the SQR. This adaptive operation leads to very small maximum error distances of the approximate divider and SQR circuits, as shown by a theoretical error analysis. The proposed 16/8 approximate divider using an 8/4 exact array divider is $2.5\times$2.5× as fast but only consumes 34.42 percent of the power of the accurate design. Compared to the accurate 16-bit array SQR circuit, the approximate design with a 6-bit radicand is $3.9\times$3.9× as fast and consumes 20.66 percent of the power. The approximate SQR circuit using a 6-bit lookup table-based SQR circuit consumes 7.15 percent of the power of its corresponding accurate design. The proposed designs outperform other approximate designs in image processing applications including change detection (for the divider), envelope detection (for the SQR circuit) and image reconstruction (for both designs).

Square root circuit using FGMOS translinear principle

A novel square root circuit using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. FGMOS transistors are being utilized in a number of new and exciting analog applications. These devices are available in standard CMOS technology because they are being widely used in digital circuits. FGMOS structures are also known as multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. Thus floating gate devices are now finding wider applications by analog researchers. The FGMOS drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only four FGMOS transistors in proposed square-root circuit. The main feature of this remarkably simple square root circuit is to reduce the errors generated by the second order effects in the current mode circuits employing translinear loop.

Design of Low Power Current Mode Square-Root Circuit

Analog circuits have been viewed as a voltage dominated type of signal processing. With the advent of CMOS technology, shrinking feature size, and reduction of supply voltage a new class of circuits developed: currentmode circuits. Among current-mode circuits “Translinear circuits” is one of the important and emerging research interests for low power analog designers. It is the practical means of implementing nonlinear signal processing functions. The performance of analog circuits strongly depends upon techniques used to exploit the characteristics of the transistors. In this paper, using exponential current-voltage relationship of MOS transistor when biased in subthreshold-mode, a square-root circuit is proposed. The circuit simulations were carried on TSMC 0.18 micrometer technology using ELDO Simulator.

New Squaring and Square-rooting Circuits Using Cdba

One new squaring and two new square-rooting circuits based on CDBAs have been introduced. The new squarer circuit consists of a CDBA, two NMOS transistors and one resistor. On the other hand, the first square-rooting circuit consists of two CDBAs, two NMOS transistors while the second square- rooting circuit consists of only a single CDBA, two NMOS transistors and two PMOS transistors. The proposed circuits exhibit wide input voltage range, very small error and offer low output impedance to facilitate easy cascading without requiring additional buffers. PSPICE simulation results are included which confirm the practical workability of the new circuits.

Anew Square-Root Circuit Using Short Channel MOSFETs with Compensation for Error Resulting from Carrier Mobility Reduction

Anew Square-Root Circuit Using Short Channel MOSFETs with Compensation for Error Resulting from Carrier Mobility Reduction

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

Fifth Order Butterworth Low Pass Square-Root Domain Filter Design

In this study, two different fifth order square-root domain low pass Butterworth filters are designed. First filter is designed directly from fifth order transfer function. Second filter is obtained by cascading one first order and two second order filters. Both filters are designed by using state space synthesis method and constituted by current mirrors, square-root circuits, current sources and capacitors. Proposed filters are simulated by PSpice using 3V supply voltage and 0.35µm CMOS technology parameters. Both filters simulation results are compared. . Ill. 6, bibl. 12 (in English; abstracts in English and Lithuanian). http://dx.doi.org/10.5755/j01.eee.115.9.749

Simple Current-Mode Square-Rooting Circuit with Temperature Compensation Using Only OTAs

A simple current-controlled current-mode square-rooting circuit with temperature compensation employing operational transconductance amplifiers (OTAs) as active elements is proposed. It has been designed by using only four OTAs, without the employment of additional passive elements. The current gain of the proposed circuit can be electronically controlled, thanks to the tuning property of the OTA. Simulation and experimental results are obtained to verify the theoretical analysis of the proposed circuit technique.

Square-rooting and absolute function circuits using operational amplifiers

A method for implementing square-rooting and absolute function circuits using operational amplifiers (opamps) as only active elements is introduced. The realisation technique is provided through the use of the opamp supply-current sensing, which utilises an inherently quadratic characteristic of the opamp class-AB output stage. The proposed circuits are attractive in terms of simple configuration and low cost. The performances of the circuits are discussed in detail. Experimental results demonstrating the characteristics of the circuits using commercially available opamps are also included.

Novel high-precision current-mode multiplier/divider

In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 μm CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.

NEGATIVE RESISTANCE ACTIVE RESISTOR WITH IMPROVED LINEARITY AND FREQUENCY RESPONSE

An original active resistor circuit will be presented. The main advantages of the new proposed implementations are the improved linearity, small area consumption and improved frequency response. An original technique for linearizing the I(V) characteristic of the active resistor will be proposed, based on the utilization of a new linear differential amplifier, and on a current-pass circuit. The linearization of the original differential structure is achieved by compensating the quadratic characteristic of the MOS transistor operating in the saturation region by an original square-root circuit. The errors introduced by the second-order effects will be strongly reduced, while the circuit frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 0.35 μm CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (± 500 mV) and a small value of the supply voltage (± 3 V).

Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490MHz and a supply voltage (VDD) of 0.75V was 104.1µW, i.e., 21.6% that (482.3µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51nW, which was only 1.69% that (1, 153nW) of the conventional SR circuit.

Novel high-precision current-mode circuits based on the MOS-translinear principle

In this paper, a method to reduce the errors generated by the second order effects in the current-mode circuits employing MOS translinear loop is proposed. Using this method a square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed and presented. They are suitable for standard CMOS fabrication and analog systems.

A New Translinear-Based Dual-Output Square-Rooting Circuit

A new wide input range square-rooting circuit is presented. The proposed circuit consists of a dual translinear loop, an absolute value circuit, and current mirrors. A current-mode technique is used to provide wide input range with simple circuitry. The output signal of the proposed circuit is the current which is proportional to the square root of input current. The proposed square-rooting circuit was confirmed by using PSpice simulator program. The simulation results demonstrate that the proposed circuit provides the excellent temperature stability with wide input current range.