SQNR Performance Research Articles

Modular Arithmetic CPM for SDR Platforms

This brief presents a new Continuous Phase Modulation (CPM) module for multi- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$h$ </tex-math></inline-formula> transmission based on modular arithmetic processing. It is well known that CPM systems are sensitive to changes in the modulation index, which is implied when fixed-point format is used in the hardware implementation. In this scenario, modular arithmetic allows a more accurate signal processing regarding SQNR performance. This proposal has been shown to improve performance compared to other state-of-the-art methods, even when the modulation indices do not have an exact representation in a given fixed-point format. Due to its highly reconfigurable architecture, this hardware block is suitable for Software Defined Radio (SDR) platforms. A complete digital architecture is also provided. Implementation results show that the new proposal have clear advantages in terms of hardware resources and operating frequency against other CPM transmitters in open-literature.

Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4-stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2.The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

Compensation method of the excess loop delay in continuous‐time delta‐sigma analog‐to‐digital converters based on model matching approach

Continuous-time (CT) delta-sigma (Δ∑) analog-to-digital converters (ADCs) have one important constrain, namely the excess loop delay. Most excess loop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distributed random variable. To improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT Δ∑ ADCs based on the model matching method is presented in this study. Compared with previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is shown through simulation that a mean value based algorithm can improve the SQNR performance of CT Δ∑ ADCs for the most probable values of the excess loop delay.

Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces

Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is to use incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of IADCs, including single-loop and MASH architectures. When using a direct-feed-forward modulator, the IADC accumulates the residue voltage, and it is easily to implement a hybrid scheme of extended counting. Several hybrid schemes are review and discussed. A multi-step extended counting scheme is discussed for high-resolution power-efficient conversion. Optimal trade-off between high order and high oversampling ratio is critical for energy efficiency. A two-step IADC is discussed, which extends the performance of an $N$ th-order IADC close to that of a $(2N\!-\!1)$ th-order IADC, with reduced power. An implemented device uses the circuitry of a second-order IADC (IADC2) to achieve a performance close to that of a third-order IADC. The two-step operation can be extended to multi-step one, and the SQNR performance can be increased significantly. The two-step operation can be extended to multi-step operation, which can boost up the order of SQNR and further improve the energy efficiency drastically.

Ultra-long FFT를 위한 Radix-2 기반 구조

This paper compares radix-2 based structures for 32768-point FFT. Radix- structures have been widely used because the butterfly is simple and the number of multipliers can be reduced in those structures. This paper applied various radix- structures to 32768-point FFT that is representing ultra-long FFT. The ultra-long FFT has been studied much recently. This paper shows that the radix- structure is the most adequate because it shows the smallest complexity in the synthesis and the best SQNR performance. should be placed here.

Low complexity twiddle factor multiplication with ROM partitioning in FFT processor

Proposed is a low-complexity twiddle factor multiplication structure for fast Fourier transform (FFT). In an FFT implementation, the twiddle factor multiplication requires a large ROM to store the twiddle factors. In the proposed structure, the ROM is partitioned into two small ROMs, whose sum of areas is much smaller than that of the original ROM. The proposed structure requires an additional multiplier, but the multiplier is shown to be small in the experimental results. The results show that the proposed structure reduces the area of the twiddle factor multiplication by around 30% with a marginal degradation in SQNR performance.

A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation.

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications

This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.

Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of CORDIC algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-CORDIC algorithm. Finally, we present two VLSI architectures for the MVR-CORDIC algorithm. It shows that by using the proposed MVR-CORDIC algorithm, we can save 50% execution time in the iterative CORDIC structure, or 50% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC scheme.