Spread Spectrum Clock Generator Research Articles

A Spread Spectrum Clock Generator with Dual-tone Hershey-Kiss Modulation Profile

This paper presents a spread spectrum clock generator (SSCG) using a dual-tone Hershey-Kiss modulation profile. The modulation controller has two up/down counters and one delta-sigma modulator, and the output of the modulation controller is provided to a multi-modulus divider in a fractional-N PLL. The proposed SSCG is designed to operate in either single-tone modulation mode or dual-tone modulation mode. Once the targeted modulation frequency and spread ratio are given, the design variables for the SSCG can be controlled digitally. The proposed SSCG was designed and fabricated using the 65 nm CMOS process and consumes 8.5 mW while generating a 5 GHz spectrum-spread clock signal with 1.2 V supply voltage. After all design parameters are set for a 0.5% spread ratio using 30 and 33 kHz modulation frequencies, the measured EMI reduction is 24.6 dB while single-tone modulation is applied and 28.7 dB while dual-tone modulation is applied.

A Regulated Pulse Current Driver with Spread Spectrum Clock Generator

This paper presents a regulated pulse current driver with a spread spectrum clock generator (SSCG) to lower the electromagnetic interference (EMI) effect. An SSCG is used and implemented by applying a triangular wave to modulate a voltage-controlled oscillator (VCO). The results show a 7 dBm reduction in the peak power level with a frequency deviation of 10%, demonstrating that the dominate harmonic is spread and distributed to adjacent frequencies, and the magnitude of harmonics is significantly reduced. The results demonstrate that the driver with a spread spectrum clock generator would help to reduce interference in sensitive electronic components and be suitable for portable consumer electronics applications.

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode.

A 32-Step Phase-Compensated Spread-Spectrum RF-PLL With 19.44-dB EMI Reduction and 10-fs Extra RMS Jitter

Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2.

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator

A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase modulation signal is applied to the proposed charge-based discrete-time loop filter. The phase difference between the input phase modulation signal and the output clock feedback phase is sampled and applied to the control voltage of an oscillator. The loop gain of the clock generator pushes the output clock phase to accurately trace the input phase modulation signal. This article achieves 3.2% spread-spectrum modulation range and 26.51-dB spread-spectrum attenuation at 352-MHz output frequency using a 2-MHz reference frequency. The in-band modulation improves a design sensitivity, and a 298-ppm modulation range error is measured with over 140% $K_{\mathrm{ VCO}}$ perturbations. This spread-spectrum clock generator is implemented in a 0.18- $\mu \text{m}$ CMOS, and achieves 951-fsrms period jitter while consuming 9.98 mW from a 1.8-V power supply.

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

In ac motor drives, the fixed-frequency harmonic components of output voltage and current from the inverter with fixed-frequency pulsewidth modulation usually lead to electromagnetic interference (EMI). The spread spectrum clock generation (SSCG) is a widely used solution for this problem. Adjusting the switching frequency to reduce EMI is one kind of practicable scheme among SSCG methods. How to design an optimal or suitable modulation profile is a research emphasis of scholars and has been discussed in depth in many literatures. However, apart from the modulation profile, the mode and quality of carrier are also important and can be improved. In most frequency modulation methods, due to the limitation of the conventional carrier generation mode, the implementation of the new frequency instruction has to wait for the termination of the last switching period. In order to eliminate the waiting state and design a simpler algorithm, this paper has proposed a wait-free phase-continuous carrier frequency modulation (WPCFM) strategy by combining the direct digital frequency synthesizer theory and proper temporal planning of control interruptions. Besides, a theoretical analysis of WPCFM, including quantization error, frequency jitter, phase delay, and voltage distortion, has been finished. Moreover, compared with conventional methods, a more convenient, feasible, and simpler field-programmable gate array based algorithm implementation method and the control structure of WPCFM are also introduced. The analysis shows that, although WPCFM causes a slight increase of the current ripple, it can solve the partial frequency nonuniform distribution problem of the conventional method, and it has a potential value of applications in the wide band gap motor drive systems. The effectiveness of the WPCFM is verified by several sets of EMI reduction experiments where classical periodic carrier frequency modulations are applied.

P‐48: A Novel “Always‐on” Spread Spectrum Clock Technique for Reducing EMI in Display Electronics

Spread Spectrum Clock Generation (SSCG) is an important technique for EMI reduction. It is especially applicable for display electronics since modern society is increasingly equipped with growing number of myriad types of semiconductor display devices. To achieve the goal of lowering peak power, clock signal is intentionally “jittered”. This fact negatively impacts the clock signal integrity. For this reason, the common practice nowadays in industry is to turn off the SSCG function in normal work mode. It is only turned on when the device is actively tested for EMI influence in the lab. In this paper, a novel SSCG technique is presented. It is based on the emerging frequency synthesis technique of Time‐Average‐Frequency Direct Period Synthesis. Its aim is to maximize frequency modulation depth while precisely controls clock’s impact on system operation so that the SSCG function can be “always‐on”.

A Novel Spread Spectrum Clock Generation Technique: Always-On Boundary Spread SSCG

Spread spectrum clock generation (SSCG) is an important technique for electromagnetic interference reduction. To achieve the goal of lowering peak power, clock signal is intentionally “jittered.” In circuit implementation, there are mainly three ways to carry out the task of jittering the clock: voltage-controlled oscillator modulation, phase-locked loop divider dithering, and clock-period direct manipulation. From the perspective of spread result, there are three types including down spread, central spread, and up spread. Being an effective solution for lowering the harmful electromagnetic peak power, SSCG is also faced with a challenge of preserving the integrity of the clock signal. In this paper, a novel approach of always-on boundary spread is presented. It is based on time-average-frequency concept. Its aim is to maximize frequency modulation depth while precisely controls clock's impact on system operation. Theoretical analysis is performed, experimental validation is provided through an implementation on field programmable gate array (FPGA). Furthermore, a commercial product is used to demonstrate the feature of “always on” enabled by this SSCG technology.

A $\Delta\Sigma$ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( $ {f}_{{\text {LBW}}}$ ). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$ . A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System

A spread-spectrum clock generator is implemented using a nested modulation profile to reduce the peak power levels of radiated electro-magnetic emissions in display products. The display data interface is a potential source of interference, and the spread spectrum technique has been extensively used for display interfaces. The proposed nested profile can further reduce electro-magnetic interference without any degradation in the other characteristics. A test chip was fabricated using a 55-nm CMOS process, and the test results indicate a 41-dB reduction. The sensitivity of a wireless receiver to interference is tested, and the EVM results for the proposed nested profile exhibits an improvement of 1.4 dB compared to those of the triangular profile.

Design of Reliable Body Channel Communication Transceiver with Spread Spectrum Clock Generator and PNR Generator

In this work, the communication of a channel in the human body has a characteristic (time-domain) which can be measured at various distances in transmission and various frequencies of a signal by the printed circuit board-an analog frontend board (PCB-AFE) support. Besides, for the wideband signal of Body Channel Communication (BCC), a human body skin acts within a range of 1 Mb/s to 40 Mb/s as the transmission medium. This communication is more stable and attenuating low power while comparing with all another transmission medium in wireless. Moreover, due to the motion of a human body, this communication doesn't get affected. Though, the body antenna gives effects in the communication of a channel of the human body by occurs some interference. The Manchester data acts as encoder and decoder in transmitter and receiver parts respectively, in an AFE-PCB the Manchester encoder data is amplified after receiving the data from end to end channel of a human body. The data quality is improved by 7X sampler in clock data recovery (CDR) circuit. Therefore, the proposed design of reliable BCC Transceiver with SSCG and PNR Generator is processed in XilinxISE14.5, ModelSim Simulator 6.5a (Quartus II 8.1), and Micro wind software tools. It is also implemented in a XilinxXC9572XL kit. The power consumption and delay is reduced up to 90%, speed is increased up to 50% and leakage current is reduced up to 80% in the transmitter part.

A Highly Linear, AEC-Q100 Compliant Signal Conditioning IC for Automotive Piezo-Resistive Pressure Sensors

In this paper, the design of a signal conditioning analog front-end (AFE) IC for an automotive piezo-resistive type pressure sensor is presented. To improve the pressure-sensing accuracy and compensate for variations in the pressure sensor and signal conditioning IC, gauge factor calibration, digital automatic offset, and gain calibration are proposed and implemented with low power consumption. By using a high-resolution analog-to-digital converter and digital-to-analog converter, the digital automatic calibration circuit can guarantee linearity of output voltage with respect to pressure to within 0.5%. As the analog signal is converted to a digital signal, accuracy in the AFE IC improves. To improve the reliability in the automotive environment, over-voltage and reverse-voltage protection circuits are integrated with the electrostatic discharge protection circuit. Also, electromagnetic interference is reduced by using the proposed spread spectrum clock generator. The proposed design is implemented using 2P4M 0.35 μm CMOS technology with an active area of 1.94 mm × 1.94 mm. Full output ranges from 0.5 to 4.5 V. The ratiometricity error is within ±0.25% when the supply voltage is changed by ±10%. Current consumption is 4.7 mA from a 5 V supply. The output accuracy is within ±0.5% with respect to the PVT variations.

Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

This study presents a spread spectrum clock generator (SSCG) circuit for high-speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage-controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum-spreading profile. The control unit consists of an analogue charge pump-based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high-speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.

A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation

This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio ( ${\delta }$ ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a −104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.

A Design of a 92.4% Efficiency Triple Mode Control DC–DC Buck Converter With Low Power Retention Mode and Adaptive Zero Current Detector for IoT/Wearable Applications

This paper presents a retention/ pulse frequency modulation (PFM)/ pulse width modulation (PWM) mode dc–dc buck converter with adaptive zero current detector (AZCD) and spread spectrum clock generation (SSCG) for IoT/Wearable systems. The proposed dc–dc buck converter is capable of handling loads from 10 μA to 20 mA with high efficiency by applying triple mode (retention mode, PFM mode, and PWM mode), gate split technique, and AZCD. Retention mode is proposed to extend wide load range at ultralight load. Gate split technique adjusts the conduction loss and switching loss. AZCD reduces the operation duty of the high-speed comparator and avoid reverse current below light load. In IoT applications, each node communicates with other nodes through a Bluetooth low energy transceiver, which consumes very low current and is highly sensitive to supply noise. Therefore, the proposed dc–dc buck converter adopts the SSCG technique to reduce electromagnetic interference by up to 18 dB. This chip is implemented using 0.13 μm CMOS technology with an active area of $\text{820}\times \text{800}\;\mu \text{m}^{2}$ . The maximum power efficiency of the proposed dc–dc buck converter is 92.4% at a switching frequency of 2.5 MHz when the load current range is 10 to 20 mA. The input voltage range and the regulated output voltage are 2.2–3.3 and 1.7 V, respectively. In addition, the proposed dc–dc buck converter achieves over 74.2% efficiency in retention mode when the load current range is from 10 to 500 μA.

A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications

ABSTRACTIn this letter, a 6‐GHz spread spectrum clock generation for Serial AT Attachment Generation 3 (SATA—III) applications in 0.18‐pm CMOS technology is presented. The 3rd‐order loop filter is to reduce the ripple of control voltage of VCO and the loop bandwidth is 625 KHz. With the aid of second‐order delta‐sigma (ΔΣ) modulator and triangular profile counter, the division ratio of divider chain can be changed periodically. The modulation frequency is 37.04 KHz with upper bound of 19 for the triangular profile counter. The proposed circuit spreads 30‐MHz frequency range from 5.97 to 6.0 GHz with an EMI reduction of 20.3 dB. The dc power consumption is 34 mW with a chip size of 0.54 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:622–624, 2017

A spread-spectrum clock generator with direct VCO modulation in open-loop

A spread-spectrum clock generator with direct VCO modulation in open-loop

확산 스펙트럼 생성기를 이용한 적외선 카메라의 방사노이즈 저감에 관한 연구

적외선 카메라는 Mil-Std-461 항목 중 복사성 방사 잡음 시험, RE-102의 규격 만족에 어려움을 겪는다. 특히 무인항공기용 전자장비의 경우 차폐 케이블을 사용하지 않아 전자기적합성 규격 만족이 어려워 적절한 대응 설계가 필요하다. 무인정찰기용 적외선 카메라의 RE-102 시험 중 50~200 MHz 대역에서 30 dBuV/m 이상 규격을 초과하는 방사 잡음을 확인하였다. Pcb em scan 결과, 디지털 제어 신호 클록의 체배 주파수에 의한 첨두 잡음 발생을 확인하였고, 카메라의 제어 클록에 3 % 다운 스프레딩 방식의 확산 스펙트럼 클록 생성기를 적용하여 방사 잡음이 최대 22.9 dBuV/m 감소함을 확인하였다. The infrared camera is difficult to satisfy the RE-102 specification of Mil-Std-461. Especially, in the case of UAV electronics, shielded cable is not used, so it is difficult to meet the electromagnetic compatibility standard. In the RE-102 test of the IR camera for UAV, radiated noise exceeding 30 dBuV/m was observed in the range of 50 MHz to 200 MHz. As a result of pcb em scan, peak noise which caused by the harmonic frequency of the digital control signal clock was observed. Radiated noise was reduced by up to 22.9 dBuV/m by applying the spread spectrum clock generator(SSCG) with 3 % down spreading method to the camera control clock.

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines

NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Existing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maximum working frequency. This paper proposes a novel glitch-free NAND-based DCDL that joins the advantages of previously proposed topologies: uses only a single flip-flop for each DE (reducing area and power) and has relaxed timing requirements (allowing easy integration in applications like SSCG). In the paper, the glitch-free operation of the proposed circuit is firstly demonstrated theoretically and then verified experimentally, with the help of an SSCG built using proposed DCDL and implemented in 28 nm CMOS. Simulation results show that proposed DCDL results in a more that 30 % reduction of the power dissipation and a >20 % reduction in area occupation with respect to double flip-flop DCDL, without any timing constraints penalty.