Split-radix Fast Fourier Transform Research Articles

A low-power twiddle factor addressing architecture for split-radix FFT processor

The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture.

A Depth-First Iterative Algorithm for the Conjugate Pair Fast Fourier Transform

The Split-Radix Fast Fourier Transform has the same low arithmetic complexity as the related Conjugate Pair Fast Fourier Transform. Both transforms have an irregular datapath structure which is straightforwardly expressed only in recursive forms. Furthermore, the conjugate pair variant has a complicated input indexing pattern which requires existing iterative implementations to rely on precomputed tables. It however allows optimization of the memory bandwidth as it requires a single twiddle factor load per radix-4 butterfly. In existing algorithms, this comes at the cost of using additional precomputed tables or performing recursive function calls. In this paper we present two novel approaches that handle both the butterfly scheduling and the input index generation of the Conjugate Pair Fast Fourier Transform. The proposed algorithm is cache-friendly because it is depth-first, non-recursive and does not rely on precomputed index tables. In order to achieve this, we relate the butterfly execution pattern of the Split-Radix and Conjugate Pair FFTs to the binary carry sequence. Based on this finding, we describe how common integer arithmetic and bitwise operations can be used to perform input reordering and depth-first traversal of the transform datapath with O(1) space complexity.

Reconfigurable Superconducting FFT Processor Using Bit-Slice Block Share Processing Unit

We have proposed a reconfigurable high speed and very economical Rapid Single Flux Quantum (RSFQ) superconducting logic design based on the Fast Fourier Transform (FFT) Processor. We have designed a 256 – point FFT processor with the help of a bit-slicing block sharing unit. RSFQ is one of the superconducting device logics comprises of Josephson Junction. The computation complexity of this superconducting FFT is less when the number of points increased. We have proposed three different designs depending on the split radix FFT, the bit-serial radix 2 FFT, and the mixed radix FFT algorithms. The proposed design will slice the 256 – point FFT into eight 32 – point FFT each and each 32 – point FFT is divided into eight 4 – point FFT each for the reduction in hardware cost. For complex multiplication, the computation complexity of our design will be less than N/2 Log2 N for the radix 2 algorithm based on the Block share processing Unit (BSPU) and further, it is reduced for split radix & mixed radix algorithms based on BSPU based RSFQ logic. Due to this, the speed of the processor is improvised compared to general FFT algorithm based semiconductor technology. we have computed and calculated the latency at 10 GHz for our designs. The main aim of this proposed design is to reduce the complex computation time and better performance of the processor with less hardware cost. This proposed design can furthermore continue to several N2 – point by using synchronous clock tree.

Towards design and automation of a scalable split-radix FFT processor for high throughput applications

Fast Fourier Transform (FFT) is a rudimentary operation in signal processing. Modern high speed signal processing and communications standards, such as 4G LTE, 5G, Internet of Things (IoT), etc., necessitate a high throughput implementation of FFT. Moreover the FFT resolution required in aforementioned standards tends to vary with the operation mode. It is, therefore, highly desirable to have a FFT implementation that not only meets the high throughput demand but is also scalable to cater any selectable N-point FFT resolution. In this paper, our contribution is two-fold. First, we have analyzed in details the operational latency and mathematical consistency of our proposed split-radix 4/8 FFT algorithm which is comparable in latency with radix-8 algorithm but is considerably less complex for large-size FFTs. Second, we have developed a JAVA-based automation tool that generates high level implementation details and VHDL descriptions of an adaptive N-point split-radix 4/8 FFT processor. The resulting design can then be rapidly prototyped and synthesized on different hardware platforms like Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Experimental results show that our proposed auto-generated modular design is comparable in resource usage with the hand-crafted fixed-size designs reported in the literature while providing considerable reduction in design effort and time.

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, the conventional address generation schemes of FFT data could also be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.

Simulation of 32-Point Split-Radix Multipath Delay Commutator (SRMDC) based FFT Architecture

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

A performance-efficient and datapath-regular implementation of modified split-radix fast Fourier transform

Discrete Fourier transform (DFT) finds various applications in signal processing, image processing, artificial intelligent, and fuzzy logic etc. DFT is often computed efficiently with Fast Fourier transform (FFT). The modified split radix FFT (MSRFFT) algorithm implements a length-N=2 m DFT achieving a reduction of arithmetic complexity compared to split-radix FFT (SRFFT). In this paper, a simplified algorithm is proposed for the MSRFFT algorithm, reducing the number of real coefficients evaluated from 5/8N − 2t o 15/32N − 2 and the number of groups of decomposition from 4 to 3. A implementation approach is also presented. The approach makes data-path of the MSRFFT regular similar to that of the radix-2 FFT algorithm. The experimental results show that (1) MSRFFT consumes less time on central processing units (CPUs) with sufficient cache than existing algorithms; (2) the proposed implementation method can save execution time on CPUs and general processing units (GPUs).

A Modified Multiple Alignment Fast Fourier Transform with Higher Efficiency.

Multiple sequence alignment (MSA) is the most common task in bioinformatics. Multiple alignment fast Fourier transform (MAFFT) is the fastest MSA program among those the accuracy of the resulting alignments can be comparable with the most accurate MSA programs. In this paper, we modify the correlation computation scheme of the MAFFT for further efficiency improvement in three aspects. First, novel complex number based amino acid and nucleotide expressions are utilized in the modified correlation. Second, linear convolution with a limitation is proposed for computing the correlation of amino acid and nucleotide sequences. Third, we devise a fast Fourier transform (FFT) algorithm for computing linear convolution. The FFT algorithm is based on conjugate pair split-radix FFT and does not require the permutation of order, and it is new as only real parts of the final outputs are required. Simulation results show that the speed of the modified scheme is 107.58 to 365.74 percent faster than that of the original MAFFT for one execution of the function Falign() of MAFFT, indicating its faster realization.

Scaled Radix-2/8 Algorithm for Efficient Computation of Length-$N=2^{m}$ DFTs

This paper presents a scaled radix-2/8 fast Fourier transform (FFT) (SR28FFT) algorithm for computing length- N = 2m discrete Fourier transforms (DFTs) scaled by complex number rotating factors. The idea of the SR28FFT algorithm is from the modified split radix FFT (MSRFFT) algorithm, and its purpose is to furnish other algorithms with high efficiency but without shortcomings of the MSRFFT algorithm. A novel radix-2/4 FFT (NR24FFT) algorithm and a novel radix-2/8 FFT (NR28FFT) algorithm are proposed. These two algorithms use SR28FFT to calculate their sub-DFTs of odd-indexed terms. Several aspects of the two algorithms such as computational complexity, computation accuracy, and coefficient evaluations or accesses to the lookup table all are improved. The bit-reverse method can be used for their order permutation and no extra memory is required to store their extra coefficients by the two novel algorithms, which contribute significantly to the performance of the FFT algorithms. The SR28FFT algorithm can also be applied to other algorithms whose decomposition contains sub-DFTs of powers-of-two. The Appendix presents an algorithm named SR28FFT-2 for further reducing the number of arithmetic operations, and NR24FFT and NR28FFT algorithms based on SR28FFT-2 requires fewer real operations than that required by the MSRFFT algorithm.

Generalized frequency-domain synthetic aperture focusing technique for ultrasonic imaging of irregularly layered objects

In ultrasonic nondestructive testing (NDT), the phase shift migration (PSM) technique, as a frequency-domain implementation of the synthetic aperture focusing technique (SAFT), can be adopted for imaging of regularly layered objects that are inhomogeneous only in depth but isotropic and homogeneous in the lateral direction. To deal with irregularly layered objects that are anisotropic and inhomogeneous in both the depth and lateral directions, a generalized frequency- domain SAFT, called generalized phase shift migration (GPSM), is proposed in this paper. Compared with PSM, the most significant innovation of GPSM is that the phase shift factor is generalized to handle anisotropic media with lateral velocity variations. The generalization is accomplished by computer programming techniques without modifying the PSM model. In addition, SRFFT (split-radix fast Fourier transform) input/output pruning algorithms are developed and employed in the GPSM algorithm to speed up the image reconstructions. The experiments show that the proposed imaging techniques are capable of reconstructing accurate shapes and interfaces of irregularly layered objects. The computing time of the GPSM algorithm is much less than the time-domain SAFT combined with the ray-tracing technique, which is, at present, the common method used in ultrasonic NDT industry for imaging layered objects. Furthermore, imaging regularly layered objects can be regarded as a special case of the presented technique.

An Innovative Fast Algorithm and Structure Design for Analysis and Synthesis Quadrature Mirror Filterbanks on the SBR in DRM

This brief presents a novel fast algorithm derivation and structure design of analysis and synthesis quadrature mirror filterbanks (SQMFs) on the spectral band replication in Digital Radio Mondiale (DRM). After the preprocedure and postprocedure, a Fourier-transform-based computational kernel was required to construct two types of fast algorithms that offered certain advantages. The Proposed-I method employs a modified split-radix fast Fourier transform (FFT) for analysis quadrature mirror filterbank (AQMF) to reduce the number of additions at the last stage of the butterfly and adopts a split-radix FFT to calculate the SQMF coefficients. The Proposed-II method used the compact structure of the variable-length recursive DFT to realize the kernel procedure for the proposed fast AQMF and SQMF algorithms. In addition, a well-known lifting scheme was applied to reduce numerous multiplication and addition calculations. Compared with the original calculations for the long transform length, all multiplication, addition, and coefficient operations for the Proposed-I method (i.e., AQMF + SQMF) had 91.65%, 79.81%, and 97.22% reductions, respectively. However, for the Proposed-II method, the total reductions of multiplication, addition, and coefficient operations were 64.16%, 21.53%, and 97.12%, respectively. Compared with the fast SQMF algorithm by Huang , the Proposed-I method for SQMF reduces 58.33% of the multiplication, 65% of the addition, and 67.19% of the coefficients. Therefore, the proposed fast quadrature mirror filterbank algorithm is a better solution than other approaches for future DRM applications.

Field-Programmable Gated Array Implementation of Split-Radix Fast Fourier Transform for High Throughput

As the signal processing required in electronic warfare (EW) domain is complex and the sample rates to be handled are very high, IP cores which are freely available are not of much use. A study of various fast fourier transform (FFT) algorithms has been carried out and spit-radix FFT has been chosen to be implemented due to fewer multiplications3.This algorithm is attractive to be implemented using field-programmable gated array (FPGA). This paper presents split-radix FFT algorithm for implementation of 512-pt FFT on FPGA platform for EW applications. The algorithm is such designed that it can achieve a throughput of up to 1500 MSPS. 512-pt SRFFT is implemented using parallel pipelined architecture in order to maximize processing speed and thus achieve a throughput of 1500 MSPS with area optimization. The pipeline structure is partitioned to balance the input throughput and to optimize the available FPGA resources. The standard Cooley-Tukey radix-2 FFT algorithm requires N/2 log2 N (for N=512, 2304 multiplications)multiplications and N log2 N additions where as radix-4 FFT requires N/2 log4 N multiplications and N log2 N additions. The SRFFT presented in this paper has a multiplicative complexity of only about two-thirds that of the radix-2 FFT, and is better than the radix-4 FFT or any higher power-of-two radix as well. The initial latency is less than N clock cycles. Defence Science Journal, 2013, 63(2), pp.210 -213 , DOI:http://dx.doi.org/10.14429/dsj. 63.4266

Improved Twiddle Access for Fast Fourier Transforms

Optimizing the number of arithmetic operations required in fast Fourier transform (FFT) algorithms has been the focus of extensive research, but memory management is of comparable importance on modern processors. In this article, we investigate two known FFT algorithms, G and GT , that are similar to Cooley-Tukey decimation-in-time and decimation-in-frequency FFT algorithms but that give an asymptotic reduction in the number of twiddle factor loads required for depth-first recursions. The algorithms also allow for aggressive vectorization (even for non-power-of-2 orders) and easier optimization of trivial twiddle factor multiplies. We benchmark G and GT implementations with comparable Cooley-Tukey implementations on commodity hardware. In a comparison designed to isolate the effect of twiddle factor access optimization, these benchmarks show typical speedups ranging from 10% to 65%, depending on transform order, precision, and vectorization. A more heavily optimized implementation of GT yields substantial performance improvements over the widely used code FFTW for many transform orders. The twiddle factor access optimization technique can be generalized to other common FFT algorithms, including real-data FFTs, split-radix FFTs, and multidimensional FFTs.

Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems

This paper presents a CORDIC (Coordinate Rotation Digital Computer)-based split-radix fast Fourier transform (FFT) core for OFDM systems, for example, Ultra Wide Band (UWB), Asymmetric Digital Subscriber Line (ADSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting - Terrestrial (DVB-T), Very High Bitrate DSL (VHDSL), and Worldwide Interoperability for Microwave Access (WiMAX). The high-speed 128/256/512/1024/2048/4096/8192-point FFT processor has been implemented by 0.18 @mm (1p6m) at 1.8 V, in which all the control signals are generated internally. This programmable FFT processor outperforms the conventional ones in terms of both power consumption and core area.

A General Class of Split-Radix FFT Algorithms for the Computation of the DFT of Length-$2^{m}$

In this paper, a general class of split-radix fast Fourier transform (FFT) algorithms for computing the length-2m DFT is proposed by introducing a new recursive approach coupled with an efficient method for combining the twiddle factors. This enables the development of higher split-radix FFT algorithms from lower split-radix FFT algorithms without any increase in the arithmetic complexity. Specifically, an arbitrary radix-2/2s FFT algorithm for any value of s, 4les sles m, is proposed and its arithmetic complexity analyzed. It is shown that the number of arithmetic operations (multiplications plus additions) required by the proposed radix-2/2s FFT algorithm is independent of s and is (2m-3)2m+1+8 regardless of whether a complex multiplication is carried out using four multiplications and two additions or three multiplications and three additions. This paper thus provides a variety of choices and ways for computing the length-2m DFT with the same arithmetic complexity.

Memory-efficient and high-speed split-radix FFT/IFFT processor based on pipelined CORDIC rotations

The author presents a CORDIC-based split-radix fast Fourier transform (FFT)/inverse FFT (IFFT) processor dedicated to the computation of 2048/4096/8192-point discrete Fourier transforms (DFTs). The arithmetic unit of a butterfly processor and a twiddle factor generator are based on a CORDIC algorithm. An efficient implementation of the CORDIC-based split-radix FFT algorithm is demonstrated. The chip of 2048/4096/8192-point FFT/IFFT core processor is fabricated in a 0.18 µm CMOS technology. The core size is 4860×7883 µm2 and contains about 200 822 gates for logic and memory, and the power dissipation is 350 mW with a clock rate of 150 MHz at 1.8 V. All control signals are generated internally on-chip. The processor performs 8192-point FFT/IFFT every 138 µs and 2048-point FFT/IFFT every 34.5 µs, respectively, which exceeds orthogonal frequency division multiplexer symbol rates. The modified-pipelining CORDIC arithmetic unit is employed for complex multiplication. A CORDIC twiddle factor generator is proposed and implemented for reducing the size of ROM required for storing the twiddle factors. Compared with conventional FFT implementations, the power consumption is reduced by 25%.

A New Radix-<tex>$2/8$</tex>FFT Algorithm for Length-<tex>$qtimes 2^m$</tex>DFTs

In this paper, a new radix-2/8 fast Fourier transform (FFT) algorithm is proposed for computing the discrete Fourier transform of an arbitrary length N=q/spl times/2/sup m/, where q is an odd integer. It reduces substantially the operations such as data transfer, address generation, and twiddle factor evaluation or access to the lookup table, which contribute significantly to the execution time of FFT algorithms. It is shown that the arithmetic complexity (multiplications+additions) of the proposed algorithm is, in most cases, the same as that of the existing split-radix FFT algorithm. The basic idea behind the proposed algorithm is the use of a mixture of radix-2 and radix-8 index maps. The algorithm is expressed in a simple matrix form, thereby facilitating an easy implementation of the algorithm, and allowing for an extension to the multidimensional case. For the structural complexity, the important properties of the Cooley-Tukey approach such as the use of the butterfly scheme and in-place computation are preserved by the proposed algorithm.

High-speed and low-power split-radix FFT

This paper presents a novel split-radix fast Fourier transform (SRFFT) pipeline architecture design. A mapping methodology has been developed to obtain regular and modular pipeline for split-radix algorithm. The pipeline is repartitioned to balance the latency between complex multiplication and butterfly operation by using carry-save addition. The number of complex multiplier is minimized via a bit-inverse and bit-reverse data scheduling scheme. One can also apply the design methodology described here to obtain regular and modular pipeline for the other Cooley-Tukey-based algorithms. For an N(= 2/sup n/)-point FFT, the requirements are log/sub 4/ N - 1 multipliers, 4log/sub 4/ N complex adders, and memory of size N - 1 complex words for data reordering. The initial latency is N + 2 /spl middot/ log/sub 2/ N clock cycles. On the average, it completes an N-point FFT in N clock cycles. From post-layout simulations, the maximum clock rate is 150 MHz (75 MHz) at 3.3 V (2.7 V), 25/spl deg/C (100/spl deg/C) using a 0.35-/spl mu/m cell library from Avant!. A 64-point SRFFT pipeline design has been implemented and consumes 507 mW at 100 MHz, 3.3 v, and 25/spl deg/C. Compared with a radix-2/sup 2/ FFT implementation, the power consumption is reduced by an amount of 15%, whereas the speed is improved by 14.5%.

An extended split-radix FFT algorithm

An extended split-radix fast Fourier transform (FFT) algorithm is proposed. The extended split-radix FFT algorithm has the same asymptotic arithmetic complexity as the conventional split-radix FFT algorithm. Moreover, this algorithm has the advantage of fewer loads and stores than either the conventional split-radix FFT algorithm or the radix-4 FFT algorithm.

Real-time FFT algorithm applied to on-line spectral analysis

On-line running spectral analysis is of considerable interest in many electrophysiological signals, such as the EEG (electroencephalograph). This paper presents a new method of implementing the fast Fourier transform (FFT) algorithm. Our "real-time FFT algorithm" efficiently utilizes computer time to perform the FFT computation while data acquisition proceeds so that local butterfly modules are built using the data points that are already available. The real-time FFT algorithm is developed using the decimation-in-time split-radix FFT (DIT sr-FFT) butterfly structure. In order to demonstate the synchronization ability of the proposed algorithm, the authors develop a method of evaluating the number of arithmetic operations that it requires. Both the derivation and the experimental result show that the real-time FFT algorithm is superior to the conventional whole-block FFT algorithm in synchronizing with the data acquisition process. Given that the FFT sizeN=2 r , real-time implementation of the FFT algorithm requires only 2/r the computational time required by the whole-block FFT algorithm.