Spl Reg Research Articles

Radial Mode Piezoelectric Transformer Design for Fluorescent Lamp Ballast Applications

In a ballast circuit, the piezoelectric transformer (PT) is used to replace the conventional inductor-capacitor resonant tank saving valuable space and cost. During circuit operation, a very high voltage is required to initially ignite the lamp while during sustained operation the voltage requirements are significantly reduced. With ballast in mind, a design process has been developed to optimize a radial mode piezoelectric transformer or Transoner/sup /spl reg// to fit a specific application while simultaneously providing highly efficient performance and the capability to provide ZVS to the switches. The design procedure was verified by a custom-designed PT operating in a 32-W ballast.

Upper layer enhancements for fast call setup in cdma2000 revision D

Fast call setup (FCS) technology, a recent enhancement in revision D of cdma2000/sup /spl reg// in 3rd generation partnership project 2 (3GPP2), is a set of mechanisms for reducing call setup latency. FCS technology comprises MS tracking mechanisms, channel assignment procedures, paging mechanisms, and traffic channel initialization procedures. The combination of these techniques contributes to the improvement of the overall call setup delay. This article discusses the functional aspects of these enhancements, and their quantitative and qualitative performance.

Broadcast and multicast services in cdma2000

A proposed broadcast and multicast system design for the third-generation cdma2000/sup /spl reg// cellular system is described. Network, signaling, and physical layer aspects of the design are proposed to provide an efficient, scalable, and practical method to support one-to-many delivery of different contents.

Cdma2000/sup /spl reg// high rate broadcast packet data air interface design

The Third Generation Partnership Project 2 recently baselined the specification for a cdma2000/sup /spl reg// high-rate broadcast packet data air interface ("cdma2000 High Rate Broadcast-Multicast Packet Data Air Interface Specification", 3GPP2 C.50054). The standard allows high-speed delivery of packet data to multiple access terminals. The article describes the air interface design adopted by 3GPP2, and presents simulation results that predict the performance of the high-speed broadcast system.

Optical phase-locked loop for coherent detection optical receiver

A novel subcarrier-based optical phase-locked loop (SC-OPLL/sup /spl reg//), with off-the-shelf optical components, is presented and demonstrated. The method, based on a continuous-wave laser and optical subcarrier modulation using a standard LiNbO/sub 3/ Mach-Zehnder modulator, allows easier practical implementation than the previously proposed OPLL circuits based on laser direct modulation.

A 400-MT/s 6.4-GB/s multiprocessor bus interface

This paper describes the design of a system bus interface for the 130-nm Itanium/sup /spl reg//2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.

PET and SPECT performance of the Siemens HD3 E.Cam/sup duet//spl reg/: a 1" Na(I) hybrid camera

Siemens has recently developed a new PET/SPECT dual-head camera, the e.cam/sup duet//spl reg/. This camera employs two HD3 detectors with 2.54 cm (1") deep Na(I) segmented crystals. This design, relatively new for Na(I), is aimed at increasing the stopping power for 511 keV /spl gamma/ rays, while maintaining good spatial resolution for SPECT. The PET performance of this camera was evaluated using the new NEMA NU2-2001 specifications. The effect of the thicker crystal on the camera's performance in the single photon acquisition mode was assessed by comparing its resolution and sensitivity to that obtained with a standard gamma camera with a 0.9525 cm (3/8") deep crystal. The Siemens e.cam was selected for this purpose as it is a very similar dual-head variable-angle system with several hardware and software elements identical to the e.cam/sup duet//spl reg/ camera.

Influence of shed parameters on the aging performance of silicone rubber insulators in salt-fog

The paper presents the results of a study on the effect of shed design on the aging performance of silicone rubber (SIR) insulators in salt-fog. The experiments on a single shed design at 35 V/mm average stress and 0.25 S/m salt-fog conductivity level are reported. Shed diameter, location and inclination angle are the parameters investigated in the study. The low frequency harmonics of the leakage current, early aging period, equivalent salt deposit density (ESDD), and physical damage are used to evaluate the aging performance of various designs. Insulators having sheds with 100 mm diameter show a better performance than those having 80, 60 and 40 mm diameter sheds. The inclination angle of the sheds is shown to have a significant effect in reducing the leakage current to a very low value but simulation results using FEMLAB/sup /spl reg// show that a steep inclination angle results in field enhancement beneath the shed that may lead to corona damage of the shed. A cup shaped design for the shed is shown to have a low leakage current level and a low field enhancement beneath the shed.

Accepted from open call - Forward high-speed wireless packet data service in is-2000 - 1xev-dv

This article describes enhancements to the physical layer design of single-carrier (1×) cdma2000/sup /spl reg// wireless networks introduced by Revision C of the IS-2000 standard (commonly referred to as 1×EV-DV). These improvements are mainly for the support of high-speed wireless packet data service on the forward (base station to mobile station) link. A new shared channel, the forward packet data channel, F-PDCH, is introduced to significantly increase spectral efficiency. This is accomplished through smart, channel-dependent scheduling of base station, BS, resources by taking advantage of the delay-tolerant nature of data traffic. This shared channel utilizes fast link adaptation through adaptive modulation and coding supported by the feedback of channel quality information. A form of hybrid ARQ type II technique commonly referred to as asynchronous adaptive incremental redundancy compensates for frame error events due to imperfect link adaptation. The impact of the new channel on voice capacity of the system is designed to be minimal because the F-PDCH utilizes resources that are not consumed by real-time users.

Scalability of web-based electronic commerce systems

In a Web-based electronic commerce system, users browse product information offered by an online store and submit requests to purchase selected items. From the user's perspective, response time is a factor that could impact the acceptability of electronic commerce. This article is concerned with system architectures for online stores. Emphasis is placed on techniques to improve a system's capacity to support more users without suffering a noticeable degradation in response time performance. Such techniques have been investigated as part of a Canadian Institute for Telecommunications Research major project entitled Enabling Technology for Electronic Commerce Applications, developed in close collaboration with the IBM/sup /spl reg// Centre for Advanced Studies. The basic architecture of a Web-based electronic commerce system is first described along with the types of data that need to be managed. Next, an overview of existing techniques for improving system capacity is presented. Finally, highlights of research results obtained as part of the CITR electronic commerce major project are discussed.

Calculating quench propagation with ANSYS/sup /spl reg//

A commercial Finite-Element-Analysis program, ANSYS/sup /spl reg//, is widely used in structural and thermal analysis. With the program's ability to include nonlinear material properties and import complex CAD files, one can generate coil geometries and simulate quench propagation in superconducting magnets. A proof-of-principle finite element model was developed assuming a resistivity that increases linearly from zero to its normal value at a temperature consistent with the assumed B magnetic field. More sophisticated models could easily include finer-grained coil, cable, structural, and circuit details. A quench is provoked by raising the temperature of an arbitrary superconducting element above its T/sub c/. The time response to this perturbation is calculated using small time-steps to allow convergence between steps. Snapshots of the temperature and voltage distributions allow examination of longitudinal and turn-to-turn quench propagation, quench-front annihilation, and cryo-stability. Modeling details are discussed, and a computed voltage history was compared with measurements from a recent magnet test.

Design of 6.6 kV, 100 A saturated DC reactor type superconducting fault current limiter

Proposed saturated DC reactor type superconducting fault current limiter (SFCL) was designed and fabricated. The rated value was 100 V and 10 A for small scale experiment. The relationships between the one-turn voltage and the cross section of the core, the inductance value are obtained. The optimized cross section of the core was 90 mm /spl times/ 45 mm under restriction of the core manufacturer. The core material was ultra fine grain steel named FINEMET/sup /spl reg// FT-3H. The number of main winding turns was 100 and that of the control winding was also 100 turns. The wires are of NbTi superconductor with different filament diameter. We enhanced this design scheme to 6.6 kV, 100 A SFCL. The core cross section size and core gap and core length of 6.6 kV design are presented.

V-t characteristics of partial discharge inception in liquid nitrogen/ PPLP/sup /spl reg// composite insulation system for HTS cable

In this paper, we studied partial discharge (PD) inception characteristics and V-t characteristics of PD inception in liquid nitrogen (LN/sub 2/)/polypropylene laminated paper (PPLP/sup /spl reg//) composite insulation system for high temperature superconducting (HTS) cable. Experimental results revealed that the magnitude of initial PD was in the range of 2.0-30 pC irrespective of butt gap condition and the initial PD was generated at the first and third quadrant of voltage phase. PD inception electric field strength (PDIE) without butt gap was 5-10% higher than that with butt gap and thicker butt gap gave larger PDIE drop. Moreover, PDIE with butt gap depended on the butt gap thickness and the number of PPLP/sup /spl reg// layers. The reason is explained by the existing probability of weak points of electrical insulation at butt gap. Finally, lifetime indices n of V-t characteristics at PD inception were obtained as 80-100 irrespective of butt gap condition. These values showed enough flat characteristics of V-t phenomena of electrical insulation.

Electrical insulation characteristics of cold dielectric high temperature superconducting cable

For the optimization of electrical insulation design for high temperature superconducting (HTS) cable, evaluation of electrical insulation characteristics especially for butt gap of LN/sub 2/ impregnated cold dielectric (CD) which consists of the wrapped tape insulation impregnated with LN/sub 2/ plays an important role. This paper presents partial discharge (PD) inception and breakdown characteristics in LN/sub 2/ impregnated butt gap model which modeled a weak point of the wrapped tape insulation impregnated with LN/sub 2/ and cable model with short length with polypropylene laminated paper (PPLP/sup /spl reg//), Nomex/sup /spl reg// paper and cellulose paper. PD current pulse was found to have a steep rise time of /spl sim/ ns and amplitude of /spl sim/ tens /spl mu/A at PD inception voltage region. Little dependency of breakdown stress on the insulating material is found. PD inception stress is almost independent of insulation thickness of 1 to 3 mm. The requirement insulation thickness for 66 kV class HTS cable is estimated to be /spl sim/ 5 mm under PD-free condition from viewpoint of long-term reliability.

Partial discharge inception characteristics under butt gap condition in liquid nitrogen/ PPLP/sup /spl reg// composite insulation system for high temperature superconducting cable

The partial discharge (PD) inception characteristics are studied in liquid nitrogen (LN/sub 2/)/polypropylene laminated paper (PPLP/sup /spl reg//) composite insulation system for high temperature superconducting (HTS) cable. Experimental results revealed that the magnitude of the initial PD increased as the PD inception electric field strength was increased, because the injected energy increased. Initial PD was generated at the first and third quadrant of applied AC voltage phase. The probability of initial PD at the positive and negative voltage phase was almost the same. The reason is because liquid nitrogen is a nonpolar molecule and we used symmetric electrode configuration with uniform electric field distribution. Finally, it was pointed out that PD inception electric field strength (PDIE) depended on the volume of the butt gap because of the increasing probability of weak points of electrical insulation, and PDIE linearly decreased with increasing stressed volume of the butt gap in the log-log scale.

Over GHz low-power RF clock distribution for a multiprocessor digital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 /spl mu/m TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers/sup /spl reg// RO3003 high-frequency organic substrate.