Spl Delta Research Articles

A 4th Order 3.6 GS/s RF /spl Sigma//spl Delta/ ADC With a FoM of 1 pJ/bit

A 4th order RF LC-based ΣΔ ADC clocked at 3.6 GHz and centered at 900 MHz is presented. A simple design methodology is used to derive a robust architecture with a minimum number of feedback coefficients. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. An efficient algorithm for the tuning and calibration of the ΣΔ LC-based loop filter is also presented. The ADC, suitable for cognitive Software Defined Radio applications, is implemented in a standard 130 nm CMOS technology. It achieves a 52 dB SFDR and a 50 dB SNR in a 28 MHz BW and consumes only 15 mW from a 1.2 V supply. The Figure of Merit of the ADC is 1.0 pJ/bit, which is to date the best reported FoM for an RF ADC. The effect of the clock jitter on the ADC performance is also measured and presented.

A Study on Multi-Level PWM and Asynchronous /spl Sigma/ /spl Delta/ Modulations for Enhanced Bandlimited Signal Tracking in Switching Power Amplifiers

This work deals with multi-level switching amplifiers, in the context of high-efficiency power amplification for signal tracking applications. In particular, this paper evaluates the reduction in the error signal's power due to multi-level power amplification (compared to conventional two-level amplifiers) and compares the performance of two multi-level pulse modulations: PWM and Asynchronous ΣΔ Modulation. First the intrinsic bandwidth limits of multi-level switching amplifiers are inferred, to clearly state the advantages and limitations of multi-level power amplification. From the existing analyses of Pulse Width Modulation already reported in the literature, PWM is herein extended to multiple levels based on an equivalent representation, which allows to derive a closed expression for the power spectrum of multi-level PWM in bandlimited signal tracking. The Asynchronous ΣΔ Modulation is extended to multiple levels and the resulting multi-level encoding algorithm is analyzed in both time and frequency domains. The performance of both modulations is characterized and compared at different operating frequencies and using different number of levels. The main outcomes of this in-depth characterization show that, if the switching frequency is high enough, the tracking error is independent of the modulation and the switching frequency, i.e., it only depends upon the number of levels, which points out the suitability of asynchronous modulations for relatively low switching frequencies (compared to the number of levels).

Implementing a /spl Sigma/ /spl Delta/ DAC in Fixed Point Arithmetic

This paper describes a simple sigma delta (SigmaDelta) digital to analog converter (DAC) that is suitable for use on the simplest of microprocessors to generate constant level or slowly varying control voltages by taking advantage of a SigmaDelta network's intrinsic limit cycle behavior. The paper describes the properties of the converter, and shows that it is inherently stable. It also explains how the user can control the dc level of the DAC's analog output, and discusses the implementation of such a DAC on an industry standard microprocessor

Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling

This paper presents a novel algorithm for synthesis of continuous-time analog filters. The goal is to find as many "very good" design points as possible without requiring feasible designs as starting points or any other additional designer knowledge as input. This problem is challenging for present exploration-based analog-synthesis methods, including existing commercial tools, which have difficulties in locating diverse constraint-satisfying designs. The proposed algorithm conducts a three-step refinement process, in which poor-quality solution-space regions are eliminated through different strategies. It starts with the step of parameter-domain pruning, which identifies parameter subdomains that are more likely to produce many feasible solution points. Domains are found using interval arithmetic and the proposed simplified affine transformation operators. In the second step, selected variable subdomains are searched using plateau search, a novel exploration technique described in this paper. The algorithm addresses the three main types of solution-space regions: 1) convex, quasi-convex, and /spl delta/-convex regions; 2) rifts; and 3) plateau. The technique expands descendant-gradient-based search with a systematic way of sampling plateau. Finally, promising regions that remained after step 2 are further refined during the step of search with adaptive-sampling step length. Using four filter examples, experiments observed the quality of results and convergence of synthesis. Plateau search was also experimented for synthesis of two /spl Delta//spl Sigma/ modulators.

RF HBT oscillators with low-phase noise and high-power performance utilizing a (/spl lambda//4/spl plusmn//spl delta/) open-stubs resonator

This paper presents a new type of transmission-line resonator and its application to RF (microwave and millimeter-wave) heterojunction bipolar transistor (HBT) oscillators. The resonator is a parallel combination of two open stubs having length of lambda/4plusmndelta(deltaLtlambda), where lambda is a wavelength at a resonant frequency. The most important feature of this resonator is that the coupling coefficient (betaC) can be controlled by changing delta while maintaining unloaded Q-factor (Q u) constant. Choosing a small value of delta allows us to reduce betaC or equivalently to increase loaded Q-factor (Q L). Since coupling elements such as capacitors or electromagnetic gaps are not needed, betaC and QL can be precisely controlled based on mature lithography technology. This feature of the resonator proves useful in reducing phase noise and also in enhancing output power of microwave oscillators. The proposed resonator is applied to 18-GHz and 38-GHz HBT oscillators, leading to the phase noise of -96-dBc/Hz at 100-kHz offset with 10.3-dBm output power (18-GHz oscillator) and -104-dBc/Hz at 1-MHz offset with 11.9 dBm (38-GHz oscillator). These performances are comparable to or better than state-of-the-art values for GaAs- or InP-based planar-circuit fundamental-frequency oscillators at the same frequency bands

Broadband quasi-Chebyshev bandpass filters with multimode stepped-impedance resonators (SIRs)

Planar broadband bandpass filters of order up to 9 are synthesized based on the multimode property of stepped-impedance resonators (SIRs). Based on the transmission line theory, the modal frequencies of the SIRs are calculated based on the impedance and length ratios of its hi- and low-Z segments. In the synthesis, the SIR coupling schemes are determined by the split mode graphs. Using one, two, two, three, and three dual- or triple-mode SIRs, quasi-Chebyshev filters with four, six, six, eight, and nine transmission poles, respectively, are synthesized with a fractional bandwidth (BW) /spl Delta/=50%. Emphasis is placed not only on designing the I/O coupling structures for matching the external Q (Q/sub ext/) and the circuit BW, but also on matching the resonant peaks of the circuit with the nominal Chebyshev poles. Measured results of experimental circuits show good agreement with simulated responses.

Device linearity comparison of uniformly doped and /spl delta/-doped In/sub 0.52/Al/sub 0.48/As/In/sub 0.6/Ga/sub 0.4/As metamorphic HEMTs

The uniformly doped and the /spl delta/-doped In/sub 0.52/Al/sub 0.48/As/In/sub 0.6/Ga/sub 0.4/As metamorphic high-electron mobility transistors (MHEMTs) were fabricated, and the dc characteristics and the third-order intercept point (IP3) of these devices were measured and compared. Due to more uniform electron distribution in the quantum-well region, the uniformly doped MHEMT exhibits a flatter transconductance (G/sub m/) versus drain-to-source current (I/sub DS/) curve and much better linearity with higher IP3 and higher IP3-to-P/sub dc/ ratio as compared to the /spl delta/-doped MHEMT, even though the /spl delta/-doped device exhibits higher peak transconductance. As a result, the uniformly doped MHEMT is more suitable for communication systems that require high linearity operation.

Force-balance interface circuit based on floating MOSFET capacitors for micro-machined capacitive accelerometers

The feasibility of a force-balance interface based on a second-order delta-sigma (/spl Delta//spl Sigma/) modulator for capacitive sensors has been analyzed in order to delimit the requirements to assure system stability for a given set of constraints related to the sensor-modulator system. A /spl Delta//spl Sigma/ modulator based on a switched-capacitor architecture with floating MOSFET capacitors has been implemented using a 0.7-/spl mu/m CMOS process. Nonlinear effects related to voltage dependence of the floating MOSFET capacitors have been avoided using a modulator architecture based on charge integrators. The behavior of the new proposed modulator has been measured experimentally and compared with an equivalent interface made with lineal capacitors. Similar results were obtained from both systems. In both circuits, the modulator resolution was better than 14 bits at a sample frequency of 250 kHz, and oversampling ratio of 256.

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

On the /spl theta/-coverage and connectivity of large random networks

Wireless planar networks have been used to model wireless networks in a tradition that dates back to 1961 to the work of E. N. Gilbert. Indeed, the study of connected components in wireless networks was the motivation for his pioneering work that spawned the modern field of continuum percolation theory. Given that node locations in wireless networks are not known, random planar modeling can be used to provide preliminary assessments of important quantities such as range, number of neighbors, power consumption, and connectivity, and issues such as spatial reuse and capacity. In this paper, the problem of connectivity based on nearest neighbors is addressed. The exact threshold function for /spl theta/-coverage is found for wireless networks modeled as n points uniformly distributed in a unit square, with every node connecting to its /spl phi//sub n/ nearest neighbors. A network is called /spl theta/-covered if every node, except those near the boundary, can find one of its /spl phi//sub n/ nearest neighbors in any sector of angle /spl theta/. For all /spl theta//spl isin/(0,2/spl pi/), if /spl phi//sub n/=(1+/spl delta/)log/sub 2/spl pi//2/spl pi/-/spl theta//n, it is shown that the probability of /spl theta/-coverage goes to one as n goes to infinity, for any /spl delta/>0; on the other hand, if /spl phi//sub n/=(1-/spl delta/)log/sub 2/spl pi//2/spl pi/-/spl theta//n, the probability of /spl theta/-coverage goes to zero. This sharp characterization of /spl theta/-coverage is used to show, via further geometric arguments, that the network will be connected with probability approaching one if /spl phi//sub n/=(1+/spl delta/)log/sub 2/n. Connections between these results and the performance analysis of wireless networks, especially for routing and topology control algorithms, are discussed.

Cluster overlay broadcast (COB): MANET routing with complexity polynomial in source-destination distance

Routing algorithms with time and message complexities that are provably low and independent of the total number of nodes in the network are essential for the design and operation of very large scale wireless mobile ad hoc networks (MANETs). In this paper, we develop and analyze Cluster Overlay Broadcast (COB), a low-complexity routing algorithm for MANETs. COB runs on top of a one-hop cluster cover of the network, which can be created and maintained using, for instance, the Least Cluster Change (LCC) algorithm. We formally prove that the LCC algorithm maintains a cluster cover with a constant density of cluster leaders with minimal update cost. COB discovers routes by flooding (broadcasting) route requests through the network of cluster leaders with a doubling radius technique. Building on the constant density property of the network of cluster leaders, we formally prove that, if there exists a route from a source to a destination node with a minimum hop count of A, then COB discovers a route with at most O(/spl Delta/) hops from the source to the destination node in at most O(/spl Delta/) time and by sending at Most O(/spl Delta//sup 2/) messages. We prove this result for arbitrary node distributions and mobility patterns and also show that COB adapts asymptotically optimally to the mobility of the nodes. In our simulation experiments, we examine the network layer performance of COB, compare it with Dynamic Source Routing, and investigate the impact of the MAC layer on COB routing.

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of /spl Sigma/-/spl Delta/ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digital-to-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and time-local nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.

A 75-dB Image Rejection IF-Input Quadrature-Sampling SC<tex>$SigmaDelta$</tex>Modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 200-kHz signal bandwidth.

TCP smoothness and window adjustment strategy

We observe that even when the system throughput is relatively stable,end users of media-streaming applications do not necessarily experience smooth throughput, due to the unsynchronized window adjustments triggered by random congestion indications. We analyze and evaluate the negative impact of random window adjustments on smoothness, short-term fairness, and long-term fairness. We further propose an experimental congestion avoidance mechanism, namely TCP(/spl alpha/, /spl beta/, /spl gamma/, /spl delta/), based on coordinated window adjustments. The flow-level smoothness is enhanced significantly for media-streaming applications, without a cost on fairness and responsiveness. Responsiveness is even boosted when bandwidth is underutilized.

Baseband and Audio Mixed-Signal Front-End IC for GSM/EDGE Applications

A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurent's approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time /spl Sigma//spl Delta/ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16bit quality as well as high-drive buffers for 4 /spl Omega/ single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode.

On incremental sigma-delta modulation with optimal filtering

The paper presents a quantization-theoretic framework for studying incremental sigma-delta (/spl Sigma//spl Delta/) data conversion systems. The framework makes it possible to efficiently compute the quantization intervals and hence the transfer function of the quantizer, and to determine the mean square error (MSE) and maximum error for the optimal and conventional linear filters for first and second order incremental /spl Sigma//spl Delta/ modulators. The results show that the optimal filter can significantly outperform conventional linear filters in terms of both MSE and maximum error. The performance of conventional /spl Sigma//spl Delta/ data converters is then compared to that of incremental /spl Sigma//spl Delta/ with optimal filtering for bandlimited signals. It is shown that incremental /spl Sigma//spl Delta/ can outperform the conventional approach in terms of signal-to-noise-and-distortion ratio. The framework is also used to provide a simpler and more intuitive derivation of the Zoomer algorithm.

Sigma-delta (/spl Sigma//spl Delta/) quantization and finite frames

The K-level Sigma-Delta (/spl Sigma//spl Delta/) scheme with step size /spl delta/ is introduced as a technique for quantizing finite frame expansions for /spl Ropf//sup d/. Error estimates for various quantized frame expansions are derived, and, in particular, it is shown that /spl Sigma//spl Delta/ quantization of a unit-norm finite frame expansion in /spl Ropf//sup d/ achieves approximation error where N is the frame size, and the frame variation /spl sigma/(F,p) is a quantity which reflects the dependence of the /spl Sigma//spl Delta/ scheme on the frame. Here /spl par//spl middot//spl par/ is the d-dimensional Euclidean 2-norm. Lower bounds and refined upper bounds are derived for certain specific cases. As a direct consequence of these error bounds one is able to bound the mean squared error (MSE) by an order of 1/N/sup 2/. When dealing with sufficiently redundant frame expansions, this represents a significant improvement over classical pulse-code modulation (PCM) quantization, which only has MSE of order 1/N under certain nonrigorous statistical assumptions. /spl Sigma//spl Delta/ also achieves the optimal MSE order for PCM with consistent reconstruction.

High-order electromechanical /spl Sigma//spl Delta/ modulation in micromachined inertial sensors

Analysis of second-order electromechanical sigma-delta (/spl Sigma//spl Delta/) inertial sensors shows that in-band quantization error introduces a resolution penalty, which cannot be eliminated by oversampling. In addition, a tradeoff between resolution and phase compensation forces such systems to operate with reduced phase margin. This paper introduces high-order electromechanical /spl Sigma//spl Delta/ modulation as an approach, which eliminates the quantization noise overhead and allows for increased phase compensation without degrading the resolution. Quasi-linear analysis is used to evaluate the contribution of the individual noise sources to the output of the system and to examine the effect of noise interaction on the behavior of electromechanical /spl Sigma//spl Delta/ modulators.

Waveguide parameter design of graded-index plastic optical fibers for bending-loss reduction

The waveguide structure of graded-index plastic optical fibers (GI POFs), such as index profile, numerical aperture (NA), and core diameter, is appropriately designed for eliminating bending losses, even under a severe bending condition. The bending loss of GI POFs under a severe bending condition is drastically reduced when the core diameter is smaller than 200 /spl mu/m and when the NA is higher than 0.25. The bending loss of GI POFs even under a severe bending condition vanishes with a core diameter of 200 /spl mu/m and an NA of 0.24. It is experimentally confirmed for the first time that the mode coupling due to the bending induces the bending loss. The mode coupling strength before the fiber is bent affects the bending loss seriously. Moreover, the mode-coupling strength is evaluated by the propagation constant difference /spl Delta//spl beta/ between the adjacent modes. The /spl Delta//spl beta/ value, which is a function of the core diameter and NA, affects the bending loss. Therefore, based on the calculation of the /spl Delta//spl beta/, we propose a guideline for the appropriate design of waveguide parameters for GI POF, in order to suppress the bending loss.

Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models

In a generic behavioral model of an analog or mixed-signal electronic system, the internal and external signals and their interactions are formulated by more general descriptions than in commonly used behavioral models. This allows a more flexible design methodology. Whereas a behavioral model models an architecture of a system at a specific abstraction level, a generic behavioral model is built up out of generic functions that by specialization of these functions allows the modeling of a wide range of system architectures with different degrees of modeling accuracy. This enhanced abstraction level makes the approach suited for systematic analysis through refinement and architectural exploration of analog and mixed-signal building blocks and systems using computer-aided-design tools. As an application of this methodology, a generic behavioral model has been developed for continuous-time (CT) /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) together with the specialization functions to take into account all major nonidealities at different levels of detail, including effects like jitter, saturation, and weakly nonlinear distortion. The results of experiments of a SystemC implementation of the model are presented. Compared to other models for analysis, the proposed method enables high accuracy even at low abstraction levels, whereas the event-driven character of the model results in short simulation times compared to time-marching simulations of behavioral models, written for example in very-high-speed-integrated-circuit (VHSIC) Hardware Description Language Analog and Mixed Signal (VHDL-AMS) or Matlab/Simulink. The flexibility of the model is demonstrated.