Spike-timing Dependent Plasticity Learning Rule Research Articles

The switching and learning behavior of an octopus cell implemented on FPGA.

A dendrocentric backpropagation spike timing-dependent plasticity learning rule has been derived based on temporal logic for a single octopus neuron. It receives parallel spike trains and collectively adjusts its synaptic weights in the range [0, 1] during training. After the training phase, it spikes in reaction to event signaling input patterns in sensory streams. The learning and switching behavior of the octopus cell has been implemented in field-programmable gate array (FPGA) hardware. The application in an FPGA is described and the proof of concept for its application in hardware that was obtained by feeding it with spike cochleagrams is given; also, it is verified by performing a comparison with the pre-computed standard software simulation results.

A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning.

The memristor has been extensively used to facilitate the synaptic online learning of brain-inspired spiking neural networks (SNNs). However, the current memristor-based work can not support the widely used yet sophisticated trace-based learning rules, including the trace-based Spike-Timing-Dependent Plasticity (STDP) and the Bayesian Confidence Propagation Neural Network (BCPNN) learning rules. This paper proposes a learning engine to implement trace-based online learning, consisting of memristor-based blocks and analog computing blocks. The memristor is used to mimic the synaptic trace dynamics by exploiting the nonlinear physical property of the device. The analog computing blocks are used for the addition, multiplication, logarithmic and integral operations. By organizing these building blocks, a reconfigurable learning engine is architected and realized to simulate the STDP and BCPNN online learning rules, using memristors and 180 nm analog CMOS technology. The results show that the proposed learning engine can achieve energy consumption of 10.61 pJ and 51.49 pJ per synaptic update for the STDP and BCPNN learning rules, respectively, with a 147.03× and 93.61× reduction compared to the 180 nm ASIC counterparts, and also a 9.39× and 5.63× reduction compared to the 40 nm ASIC counterparts. Compared with the state-of-the-art work of Loihi and eBrainII, the learning engine can reduce the energy per synaptic update by 11.31× and 13.13× for trace-based STDP and BCPNN learning rules, respectively.

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

Neuronal avalanche dynamics regulated by spike-timing-dependent plasticity under different topologies and heterogeneities.

Neuronal avalanches, a critical state of network self-organization, have been widely observed in electrophysiological records at different signal levels and spatial scales of the brain, which has significant influence on information transmission and processing in the brain. In this paper, the collective behavior of neuron firing is studied based on Leaky Integrate-and-Fire model and we induce spike-timing-dependent plasticity (STDP) to update the connection weight through competition between adjacent neurons in different network topologies. The result shows that STDP can facilitate the synchronization of the network and increase the probability of large-scale neuron avalanche obviously. Moreover, both the structure of STDP and network connection density can affect the generation of avalanche critical states, specifically, learning rate has positive correlation effect on the slope of power-law distribution and time constant has negative correction on it. However, when we the increase of heterogeneity in network, STDP can only has obvious promotion in synchrony under suitable level of heterogeneity. And we find that the process of long-term potentiation is sensitive to the adjustment of time constant and learning rate, unlike long-term depression, which is only sensitive to learning rate in heterogeneity network. It is suggested that presented results could facilitate our understanding on synchronization in various neural networks under the effect of STDP learning rules.

Optimal Resonances in Multiplex Neural Networks Driven by an STDP Learning Rule

In this paper, we numerically investigate two distinct phenomena, coherence resonance (CR) and self-induced stochastic resonance (SISR), in multiplex neural networks in the presence of spike-timing-dependent plasticity (STDP). The high degree of CR achieved in one layer network turns out to be more robust than that of SISR against variations in the network topology and the STDP parameters. This behavior is the opposite of the one presented by Yamakou and Jost (Phys. Rev. E 100, 022313, 2019), where SISR is more robust than CR against variations in the network parameters but in the absence of STDP. Moreover, the degree of SISR in one layer network increases with a decreasing (increasing) depression temporal window (potentiation adjusting rate) of STDP. However, the poor degree of SISR in one layer network can be significantly enhanced by multiplexing this layer with another one exhibiting a high degree of CR or SISR and suitable inter-layer STDP parameter values. In addition, for all inter-layer STDP parameter values, the enhancement strategy of SISR based on the occurrence of SISR outperforms the one based on CR. Finally, the optimal enhancement strategy of SISR based on the occurrence of SISR (CR) occurs via long-term potentiation (long-term depression) of the inter-layer synaptic weights.

Investigation of STDP mechanisms for memristor circuits

Memristive systems have become popular as a research field after the experimental realization of a memristor by the HP Labs research team. Researchers have demonstrated the synaptic behavior of the memristor in addition to its nonlinear and nonvolatile characteristics. Synapses play an important role in the learning process and spike-timing-dependent plasticity (STDP) is a fundamental synaptic learning rule. Because of problems with finding the memristor on the market as a discrete circuit element, researchers have designed many types of memristor circuits to emulate memristors. However, no information is available about the STDP behavior of these designed memristor emulators. This paper investigated the STDP property of some basic memristor circuits and the mathematical and simulation results demonstrated that none of them could support the STDP learning rule.

ALSA: Associative Learning Based Supervised Learning Algorithm for SNN.

Spiking neural network (SNN) is considered to be the brain-like model that best conforms to the biological mechanism of the brain. Due to the non-differentiability of the spike, the training method of SNNs is still incomplete. This paper proposes a supervised learning method for SNNs based on associative learning: ALSA. The method is based on the associative learning mechanism, and its realization is similar to the animal conditioned reflex process, with strong physiological plausibility and rationality. This method uses improved spike-timing-dependent plasticity (STDP) rules, combined with a teacher layer to induct spikes of neurons, to strengthen synaptic connections between input spike patterns and specified output neurons, and weaken synaptic connections between unrelated patterns and unrelated output neurons. Based on ALSA, this paper also completed the supervised learning classification tasks of the IRIS dataset and the MNIST dataset, and achieved 95.7 and 91.58% recognition accuracy, respectively, which fully proves that ALSA is a feasible SNNs supervised learning method. The innovation of this paper is to establish a biological plausible supervised learning method for SNNs, which is based on the STDP learning rules and the associative learning mechanism that exists widely in animal training.

Reliable analog resistive switching behaviors achieved using memristive devices in AlO x /HfO x bilayer structure for neuromorphic systems

Human brain synaptic memory simulation based on resistive random access memory (RRAM) has enormous potential to replace the traditional von Neumann digital computer thanks to several advantages, including its simple structure, its high-density integration, and its capabilities regarding information storage and neuromorphic computing. Herein, the reliable resistive switching (RS) behaviors of RRAM are demonstrated by engineering the AlO x /HfO x bilayer structure. This allows for uniform multibit information storage. Further, the analog switching behaviors are capable of imitating several synaptic learning functions, including learning experience behaviors, short-term plasticity, long-term plasticity transition, and spike-timing-dependent plasticity (STDP). In addition, the memristor based on STDP learning rules is implemented in image pattern recognition. These results may show the potential of HfO x -based memristors for future information storage and neuromorphic computing applications.

Neuromorphic Functional Modules of Spiking Neural Network

In the current era, design and development of artificial neural networks exploiting the architecture of the human brain have evolved rapidly. Artificial neural networks effectively solve a wide range of common for artificial intelligence tasks involving data classification and recognition, prediction, forecasting and adaptive control of object behavior. Biologically inspired underlying principles of ANN operation have certain advantages over the conventional von Neumann architecture including unsupervised learning, architectural flexibility and adaptability to environmental change and high performance under significantly reduced power consumption due to heavy parallel and asynchronous data processing. In this paper, we present the circuit design of main functional blocks (neurons and synapses) intended for hardware implementation of a perceptron-based feedforward spiking neural network. As the third generation of artificial neural networks, spiking neural networks perform data processing utilizing spikes, which are discrete events (or functions) that take place at points in time. Neurons in spiking neural networks initiate precisely timing spikes and communicate with each other via spikes transmitted through synaptic connections or synapses with adaptable scalable weight. One of the prospective approach to emulate the synaptic behavior in hardware implemented spiking neural networks is to use non-volatile memory devices with analog conduction modulation (or memristive structures). Here we propose a circuit design for functional analogues of memristive structure to mimic a synaptic plasticity, pre- and postsynaptic neurons which could be used for developing circuit design of spiking neural network architectures with different training algorithms including spike-timing dependent plasticity learning rule. Two different circuits of electronic synapse were developed. The first one is an analog synapse with photoresistive optocoupler used to ensure the tunable conductivity for synaptic plasticity emulation. While the second one is a digital synapse, in which the synaptic weight is stored in a digital code with its direct conversion into conductivity (without digital-to-analog converter andphotoresistive optocoupler). The results of the prototyping of developed circuits for electronic analogues of synapses, pre- and postsynaptic neurons and the study of transient processes are presented. The developed approach could provide a basis for ASIC design of spiking neural networks based on CMOS (complementary metal oxide semiconductor) design technology.

Earliest Experience of a Relatively Rare Sound But Not a Frequent Sound Causes Long-Term Changes in the Adult Auditory Cortex.

Sensory experience during a critical period alters sensory cortical responses and organization. We find that the earliest sound-driven activity in the mouse auditory cortex (ACX) starts before ear-canal opening (ECO). The effects of auditory experience before ECO on ACX development are unknown. We find that in mouse ACX subplate neurons (SPNs), crucial in thalamocortical maturation, respond to sounds before ECO showing oddball selectivity. Before ECO, SPNs are more selective to oddball sounds in auditory streams than thalamo-recipient layer 4 (L4) neurons and not after ECO. We hypothesize that SPN's oddball selectivity can direct the development of L4 responses before ECO. Exposing mice, of either sex, before ECO to a rarely occurring tone in a stream of another tone occurring frequently leads to strengthening the adult cortical representation of the rare tone, but not that of the frequent tone. Results of control exposure experiments at multiple developmental windows that also use only a single tone corroborate the observations. We further explain the strengthening of deviant inputs before ECO and not after ECO using a binary network model mimicking the hierarchical structure of subplate and L4 neurons and response properties derived from our data, with synapses following Hebbian spike time-dependent plasticity learning rule. Information-theoretic analysis with sparse coding assumptions also predicts the observations. Thus, relatively salient low probability sounds in the earliest auditory environment cause long-term changes in the ACX.SIGNIFICANCE STATEMENT Early auditory experience can change the organization and responses of the auditory cortex in adulthood. However, little is known about how auditory experience at prenatal ages changes neural circuits and response properties. In mice at equivalent early developmental stages, we find that auditory experience of a particular kind, with a less frequently occurring sound in a stream of another sound, alters adult cortical responsiveness, specifically of the less frequent sound. However, at the previously known critical period of development, the opposite is observed, where the more frequent sound's representation is strengthened in the adult compared with the less frequent sound. We thus show that a specific type of auditory environment can influence adult auditory processing at the earliest ages.

On addressing the similarities between STDP concept and synaptic/memristive coupled neurons by realizing of the memristive synapse based HR neurons

The Spike-Time-Dependent-Plasticity (STDP) learning rule is frequently associated with the memristor structures in the neuromorphic studies, recently. In this study, after two HR neurons are coupled with a memristor based synapse structure as a unidirectional coupling; it is aimed to correlate the STDP learning rule and the memristor based synapse structure. In line of this motivation, two HR neurons (the transmitter and the receiver neurons) have been coupled with a memductance structure. After the current at the output of this memristor based synapse has been applied to the receiver neuron, a phase shift has been induced on the membrane potential of this receiver neuron. Additionally, this phase shift can be controlled by changing the ’Ron’ resistance that is a parameter of the windowing function definition of the memristor device similar to the synaptic coupling weight parameter. Since the firing times of these coupled HR neurons can be controlled by changing this ’Ron’ resistance, the STDP learning rule, which is based on the instantaneous firing time difference between the coupled neurons, has been validated as an alternative view point in here. The similarity between the pattern of the STDP learning rule and the pattern of two HR neurons coupled with the chemical and the memristor based synapses has been confirmed by comparing the numerical simulation results and it has been seen that the memristor device can be used as an alternative synapse definition in the neuromorphic studies. Finally, two HR neurons coupled with the memristor based synapse have been successfully realized by using the FPGA equipment, so an alternative neuromorphic study, which is associated with the STDP learning rule, memristor synapse and HR neurons, has been presented to the literature with this implementation.

An Adaptive STDP Learning Rule for Neuromorphic Systems.

The promise of neuromorphic computing to develop ultra-low-power intelligent devices lies in its ability to localize information processing and memory storage in synaptic circuits much like the synapses in the brain. Spiking neural networks modeled using high-resolution synapses and armed with local unsupervised learning rules like spike time-dependent plasticity (STDP) have shown promising results in tasks such as pattern detection and image classification. However, designing and implementing a conventional, multibit STDP circuit becomes complex both in terms of the circuitry and the required silicon area. In this work, we introduce a modified and hardware-friendly STDP learning (named adaptive STDP) implemented using just 4-bit synapses. We demonstrate the capability of this learning rule in a pattern recognition task, in which a neuron learns to recognize a specific spike pattern embedded within noisy inhomogeneous Poisson spikes. Our results demonstrate that the performance of the proposed learning rule (94% using just 4-bit synapses) is similar to the conventional STDP learning (96% using 64-bit floating-point precision). The models used in this study are ideal ones for a CMOS neuromorphic circuit with analog soma and synapse circuits and mixed-signal learning circuits. The learning circuit stores the synaptic weight in a 4-bit digital memory that is updated asynchronously. In circuit simulation with Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS process design kit (PDK), the static power consumption of a single synapse and the energy per spike (to generate a synaptic current of amplitude 15 pA and time constant 3 ms) are less than 2 pW and 200 fJ, respectively. The static power consumption of the learning circuit is less than 135 pW, and the energy to process a pair of pre- and postsynaptic spikes corresponding to a single learning step is less than 235 pJ. A single 4-bit synapse (capable of being configured as excitatory, inhibitory, or shunting inhibitory) along with its learning circuitry and digital memory occupies around 17,250 μm2 of silicon area.

Reliable Resistive Switching and Synaptic Behaviors Based on a TiOx‐Doped N Memristor for Information Storage and Neuromorphic Computing

Bipolar resistive switching (RS) and synaptic behaviors of resistive random access memory (RRAM) based on TiO x are demonstrated. RS uniformity is improved by introducing nitrogen into the RS layer using radio frequency sputtering in the reactive Ar/N2 ambient. The conductive mechanism is in good agreement with the space−charge‐limited conduction model. The activation energy fit by the Arrhenius equation and conductive atomic force microscopy results indicate that the conductive filaments are formed by oxygen vacancies. More importantly, reliable multilevel RRAM can be achieved by tuning the compliance current, which enables the achievement of distinguishable resistance states. Furthermore, multilevel RRAM enables the simulation of synaptic functions, such as learning−forgetting−relearning, habituation, and spike‐timing‐dependent plasticity (STDP). Image pattern recognition based on STDP learning rules using a digital memristor is demonstrated. The findings may offer a route to the development of future storage and neuromorphic computing.

Realizing diverse STDP learning rules in synaptic circuit based on memristor

Being a nonlinear circuit component with memory function, a memristor is similar to a synapse in human brain, whose conductance can be changed after electrical stimulation. It can be used to simulate a synaptic behavior in the process of learning and memory. In this work, a synaptic circuit based on memristor is realized, which includes an enhancement module, a suppression module, and a memristive synapse module. The enhancement module and the suppression module are composed of op-amps, logic gate, and analog switch, etc., while the memristive synapse module consists of a memristor and an analog switch. By inputting a pair of pulsed DC actuators in the enhancement and suppression modules, the stimulation of bio-synapse from pre-neuron to post-neuron is simulated. By adjusting the time interval between pulse input signals, it is found that the shorter the signal interval, the more remarkable the change in conductance will be achieved by the memristor, which is consistent with the change in spike-timing dependent plasticity (STDP) learning curve of bio-synapse. In order to achieve diversity of the synaptic simulation, four replacement circuits of the memristive synapse module are proposed, each of which can simulate different learning rules on its own. Therefore, the circuits can simulate four kinds of synaptic STDP learning rules, which can solve problems such as single-type simulation, harsh input conditions, etc. in synaptic circuit research, and these circuits are expected to be applied in the development of neuromorphic chips in the future.

Optimal Distribution of Spiking Neurons Over Multicore Neuromorphic Processors

In a multicore neuromorphic processor embedding a learning algorithm, a presynaptic neuron is occasionally located in a different core from the cores of its postsynaptic neurons, which needs neuron-to-target core communication for inference through a network router. The more neuron-to-target core connections, the more workload is imposed on the network router, which the more likely causes event routing congestion. Another significant challenge arising from a large number of neuron-to-core connections is data duplication in multiple cores for the learning algorithm to access the full data to evaluate weight update. This data duplication consumes a considerable amount of on-chip memory while the memory capacity per core is strictly limited. The optimal distribution of neurons over cores is categorized as an optimization problem with constraints, which may allow the discrete Lagrangian multiplier method (LMM) to optimize the distribution. Proof-of-concept demonstrations were made on the distribution of neurons over cores in a neuromorphic processor embedding a learning algorithm. The choice of the learning algorithm was twofold: a simple spike timing-dependent plasticity learning rule and event-driven random backpropagation algorithm, which are categorized as a two- and three-factor learning rule, respectively. As a result, the discrete LMM significantly reduced the number of neuron-to-core connections for both algorithms by approximately 55% in comparison with the number for random distribution cases, implying a 55% reduction in the workload on the network router and a 52.8% reduction in data duplication. The code is available on-line (https://github.com/guhyunkim/Optimize-neuron-distribution).

Classifying Melanoma Skin Lesions Using Convolutional Spiking Neural Networks With Unsupervised STDP Learning Rule

Deep learning methods have made some achievements in the automatic skin lesion recognition, but there are still some problems such as limited training samples, too complicated network structure, and expensive computational costs. Considering the inherent power-efficiency, biological plausibility and good image recognition performance of spiking neural networks (SNNs), in this paper we make malignant melanoma and benign melanocytic nevi skin lesions classification using convolutional SNNs with unsupervised spike-timing-dependent plasticity (STDP) learning rule. Efficient temporal coding, event driven learning rule and winner-take-all (WTA) mechanism together ensure sparse spike coding and efficient learning of our networks which achieve an average accuracy of 83.8%. We further propose to use feature selection to select more diagnostic features to improve the classification performance of our networks. Our SNNs with feature selection reach an average accuracy of 87.7%. Experimental results show that comparing to CNNs that need to be trained from scratch, our SNNs (with and without feature selection) not only achieve much better classification accuracies but also have much better runtime efficiency. Moreover, although the pretrained CNNs models can achieve similar running time, our proposed SNNs are more stable and easier to use than the pretrained CNNs because we do not need to try many pretrained models any more, and our SNNs also have much better classification accuracies than the pretrained CNNs. In addition, our networks have only three convolutional layers, and the complexity of the model and the parameters that need to be trained in the networks are greatly reduced. Our works show that STDP-based SNNs are very beneficial for the implementation of automated skin lesion classifiers on small portable devices.

Unsupervised Learning by Spike-Timing- Dependent Plasticity in a Mainstream NOR Flash Memory Array—Part II: Array Learning

In this article, we show that, by exploiting the program and erase conditions identified in Part I of this article, operating a mainstream NOR Flash memory array as an artificial synaptic array learning in an unsupervised manner according to the spike-timing-dependent plasticity (STDP) rule can be easily achieved. To this aim, first, a word-line and a bitline voltage scheme allowing cells to change their memory state and, in turn, their synaptic weight to mimic the STDP learning rule is presented. Then, a simple spiking neural network making use of the NOR Flash array as a synaptic array is discussed along with its basic operating waveforms. Finally, the proof of concept for unsupervised learning in the array of a signal pattern provided at the network inputs is given.

Realizing spike-timing dependent plasticity learning rule in Pt/Cu:ZnO/Nb:STO memristors for implementing single spike based denoising autoencoder

In this work, the Cu:ZnO based memristors were fabricated and modelled and its biological synaptic characteristics were realized. Phenomenon similar to long-term potentiation and long-term depression were observed in the proposed devices and spike timing dependent plasticity learning rule was established by engineering appropriate input voltage spikes, making the devices suitable for use in artificial neural networks. In order to demonstrate learning mechanism, a denoising autoencoder network was developed by incorporating the synaptic characteristics of the device along with the concept of rank coding. To evaluate the feasibility and performance of the network, images from the MNIST database for handwritten digits were employed. The training of the proposed network was accomplished by incorporating noisy images, and it was validated with images corrupted with Gaussian, Salt & Pepper and Speckle noises. Surprisingly, the obtained results demonstrated that the shape of the digits was recovered to a great extent and almost all noise in the background were removed. The accuracy of the denoising was found to be more than 90% for most cases. The proposed network shows the efficacy of ferroelectric Cu:ZnO memristors as artificial synapses in spiking neural networks, which opens up a new path towards developing future generation biologically compatible neuromorphic systems.

Mimicking the spike-timing dependent plasticity in HfO2-based memristors at multiple time scales

In this work, TiN/Ti/HfO2/W memristors have been investigated to mimic the spike-time dependent plasticity (STDP) of biological synapses at multiple time scales. For this purpose, a smart software tool has been implemented to control the instrumentation and to perform a dedicated ultra-fast pulsed characterization. Different time scales, from tens of milliseconds to hundreds of nanoseconds, have been explored to emulate the STDP learning rule in electronic synapses. The impact of such times on the synaptic weight potentiation and depression characteristics has also been discussed.

Fully Printed All-Solid-State Organic Flexible Artificial Synapse for Neuromorphic Computing.

Nonvolatile, flexible artificial synapses that can be used for brain-inspired computing are highly desirable for emerging applications such as human-machine interfaces, soft robotics, medical implants, and biological studies. Printed devices based on organic materials are very promising for these applications due to their sensitivity to ion injection, intrinsic printability, biocompatibility, and great potential for flexible/stretchable electronics. Herein, we report the experimental realization of a nonvolatile artificial synapse using organic polymers in a scalable fabrication process. The three-terminal electrochemical neuromorphic device successfully emulates the key features of biological synapses: long-term potentiation/depression, spike timing-dependent plasticity learning rule, paired-pulse facilitation, and ultralow energy consumption. The artificial synapse network exhibits an excellent endurance against bending tests and enables a direct emulation of logic gates, which shows the feasibility of using them in futuristic hierarchical neural networks. Based on our demonstration of 100 distinct, nonvolatile conductance states, we achieved a high accuracy in pattern recognition and face classification neural network simulations.