SPICE-based Circuit Simulators Research Articles

NUMA-aware parallel sparse LU factorization for SPICE-based circuit simulators on ARM multi-core processors

In circuit simulators that resemble the Simulation Program with Integrated Circuit Emphasis (SPICE), one of the most crucial steps is the solution of numerous sparse linear equations generated by frequency domain analysis or time domain analysis. The sparse direct solvers based on lower-upper (LU) factorization are extremely time-consuming, so their performance has become a significant bottleneck. Despite the existence of some parallel sparse direct solvers for circuit simulation problems, they remain challenging to adapt in terms of performance and scalability in the face of rapidly evolving parallel computers with multiple NUMA hardware based on ARM architecture. In this paper, we introduce a parallel sparse direct solver named HLU, which re-examines the performance of the parallel algorithm from the viewpoint of parallelism in pipeline mode and the computing efficiency of each task. To maximize task-level parallelism and further minimize the thread waiting time, HLU devises a fine-grained scheduling method based on an elimination tree in pipeline mode, which employs depth-first search (DFS-like) to iteratively search for parent tasks and then place dependent tasks in the same task queue. HLU also suggests two NUMA node affinity strategies: thread affinity optimization based on NUMA nodes topology to guarantee computational load balancing and data affinity optimization to enable effective memory placement when threads access data. The rationality and effectiveness of the sparse solver HLU are validated by the SuiteSparse Matrix Collection. In comparison with KLU and NICSLU, the experimental results and analysis show that HLU attains a speedup of up to 9.14× and 1.26x (geometric mean) on a Huawei Kunpeng 920 Server, respectively.

Static, Dynamic, and Signal-to-Noise Analysis of a Solid-State Magnetoelectric (Me) Sensor with a Spice-Based Circuit Simulator

Modeling the non-electrical processes by equivalent electrical circuits is a widely known and successfully used technique in research and development. Although finite element methods software development has supplanted electrical analogy techniques due to greater accuracy and intuitiveness in recent decades, the modeling of physical processes based on analogies has several advantages in some cases. Representation of physical processes in the form of lumped circuits and graphs allows researchers to estimate the system with an alternative view, use standardized methods for solving electrical circuits for non-electrical systems, and, most importantly, allows us to use electrical circuit simulators with their unique capabilities. Of particular interest for using the analogy technique are systems that include electronic components along with components belonging to other physical domains, such as mechanical, thermal, magnetic, and others. A solid-state magnetoelectric (ME) sensor equipped with a charge amplifier is proposed in this study as an example of analysis using the equivalent electrical circuit and simulating these circuits using SPICE-based circuit simulators. Sensor analysis is conducted with an emphasis on noise budgeting and optimizing the sensor’s signal-to-noise ratio and resolution. In addition, the steady state, the phasor, and transient types of analyses were employed to study the static and dynamic behavior of the system. Validation of the model using analytical calculations and comparison with experimental data demonstrated superior results.

A holistic fast and parallel approach for accurate transient simulations of analog circuits

The accurate analog simulation of critical circuit parts is a key task in the R&D process of integrated circuits. With the increasing complexity of integrated circuits it is becoming cumulatively challenging to simulate in the analog domain and within reasonable simulation time. Previous speedup approaches of the SPICE (Simulation Program with Integrated Circuit Emphasis) analog circuit simulator included either solver improvements and speedup or model order reduction of the semiconductor devices.In this paper we present a comprehensive approach to significantly speedup a SPICE-based analog circuit simulator while keeping the single-rate characteristic of time domain simulations. The novelty of our approach consists in the combination and extension of existing approaches in a unique way, enabling fast transient SPICE-level simulations. The main component of our approach is the circuit partitioner that combines relevant aspects from circuit theory and linear algebra in a unifying way. This enables the construction of an efficient and parallel BBD (bordered block diagonal) solver. Furthermore, this BBD structure allows for intrinsic model order reduction of the partitions during the Newton iteration, transforming the Newton method to a Quasi-Newton method.For mid-sized and large-sized circuits our BBD approach leads to significant sequential and parallel accelerations of transient simulations. Additional speedup can be gained from our block-bypass strategies exploiting the latency in the partitioned circuit. Altogether our approach leads to a speedup of up to two orders of magnitude compared to the state-of-the-art KLU solver while maintaining SPICE-level accuracy.

Dynamic Modeling and Power Loss Analysis of High-Frequency Power Switches Based on GaN CAVET

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency.

A methodology for automated analysis of SPICE simulation data

The paper presents an automation methodology for SPICE-based circuit simulation analysis. Generally, circuit simulators provide text-based output files which require volcanic and error prone efforts during circuit validation process. The task become more arduous for evaluating circuit performance for variant design parameters involved. A typical meticulous analysis process may contain several thousands of data entries which need to be handled with complete conscientiousness. Furthermore, while examining the circuits with said variant parameters the general GUI-based interface provided with CAD tool proves to be meagre for handling the colossal and monstrous data created. To optimise analysis process authors have proposed a methodology. The authors have integrated different distributed flow assisting the designer to analyse and generate charts making use features in Microsoft Excel. From the adoption of the proposed system the authors have successfully reduced the task involved, in the sense of auto generating the Excel-based data for analytical analysis and inferring process.

A Novel Active Frequency Selective Surface With Wideband Tuning Range for EMC Purpose

A novel symmetric anchor-shaped active frequency selective surface (AFSS) with a wide tuning frequency range is proposed. Varactor diodes are used as the active tuning components at the center of each AFSS unit. The equivalent circuit model of the AFSS unit is extracted. SPICE-based circuit simulation and full-wave simulation are compared to predict the resonant frequency. A wide tunable frequency range from 1.76 to 2.45 GHz with a relative bandwidth of 33% is achieved. A prototype of AFSS is fabricated and tested. The measurement result is consistent with the simulation. The design has low power consumption and is potentially used for selectively shielding or reusing of GSM, TD-SCDMA, or Wi-Fi spectrums.

Advanced Circuit Simulation Using Multisim Workbench

Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.

Characterization of SiC JFETs and its Application in Extreme Temperature (over 450°C) Circuit Design

In order to facilitate the circuit design and simulation at extreme temperatures, APEI, Inc. fully characterized a custom-built SiC VJFET transistor at temperatures up to 525 °C and built a Spice model based on the characterization data. The temperature effects were also formulized in this Spice model to ensure its uniform applicability over the entire temperature range. Test circuits of a differential amplifier and a multivibrator were built and tested from room temperature up to 450 °C to validate the proposed SiC JFET model, which could be widely applied in Spice based circuit simulation packages.

High-Frequency-Measurement-Based Circuit Modeling and Power/Ground Integrity Evaluation of Integrated Circuit Packages

The frequency-variant characteristics of a pair of package power and ground net are experimentally investigated and modeled by using frequency-variant grid-type equivalent circuits, where each cell of the grid is modeled with vertically stacked RLC-ladder circuits. Various test patterns are designed and fabricated by employing a ball grid array (BGA) package process. Then the test patterns are characterized by using impedance analyzer, time domain reflectometry and time domain transmission (TDR/TDT), and vector network analyzer (VNA). Based on the experimental characterizations, not only are material constants and circuit model parameters determined, but also the conductor roughness and other frequency-variant effects are modeled. It is shown that the SPICE-based circuit simulation using the proposed circuit model has an excellent agreement with the measurement data in the range of 100 MHz - 15 GHz. Then, it is also shown that the various types of package performance evaluations can be very efficiently as well as accurately achieved with the proposed technique.

Modeling and analysis of power distribution networks for gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.

Subspace Based Identification of Broadband Electrical Models from Frequency Response Data

Abstract The generation of broadband equivalent circuit models for time-domain analysis of complex structures or components characterized by frequency-dependent network parameters is of great interest in microwave theory. In this paper, a recently developed frequency-domain subspace identification algorithm is applied to generate multi-port circuit models for passive microwave devices characterized by admittance, impedance, or scattering parameter data. The proposed method combines non-parametric minimal order realization and efficient passivity check. It is suitable for simulating linear sub-networks characterized by frequency response data in a general circuit environment consisting of lumped/distributed elements and nonlinear devices. The synthesized networks are compatible with SPICE-based circuit simulators, as is demonstrated by numerical examples.

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.

Analysis and reduction of signal readout circuitry temporal noise in CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 /spl mu/m CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data.