Speed Degradation Research Articles

Reservoir computing with a random memristor crossbar array.

Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays (MCAs) with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in tasks of recognizing digit images and waveforms. This work indicates that the "nonidealities" of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.

A wireless controlled robotic insect with ultrafast untethered running speeds

Running speed degradation of insect-scale (less than 5 cm) legged microrobots after carrying payloads has become a bottleneck for microrobots to achieve high untethered locomotion performance. In this work, we present a 2-cm legged microrobot (BHMbot, BeiHang Microrobot) with ultrafast untethered running speeds, which is facilitated by the complementary combination of bouncing length and bouncing frequency in the microrobot’s running gait. The untethered BHMbot (2-cm-long, 1760 mg) can achieve a running speed of 17.5 BL s−1 and a turning centripetal acceleration of 65.4 BL s−2 at a Cost of Transport of 303.7 and a power consumption of 1.77 W. By controlling its two front legs independently, the BHMbot demonstrates various locomotion trajectories including circles, rectangles, letters and irregular paths across obstacles through a wireless control module. Such advancements enable the BHMbot to carry out application attempts including sound signal detection, locomotion inside a turbofan engine and transportation via a quadrotor.

Theoretical study of the influence of GaOx interfacial layer on the GaN/SiO2 interface property

The spontaneous formation of a Ga-oxide (GaOx) intermediate layer at the GaN/SiO2 interface has been reported during the SiO2 deposition on the GaN substrate. In this study, we have performed first-principles calculations and unveiled atomic and electronic structures of the GaN/SiO2 interface with 1-nm thick GaOx intermediate layer. Our calculations show that the top-layer Ga atoms on the GaN side are terminated with the O atoms on the GaOx side, leading to the clean GaN/GaOx interface and the absence of the electronic state in the midgap region. However, strongly localized states, which are originated from O atoms lone-pair orbitals in the –GaOSi– local structures, emerge in the gap near the valence-band maximum of GaN. These in-gap states become hole traps in GaN MOS devices, leading to a degradation in device controllability and operational speed.

Towards quantifying the communication aspect of resilience in disaster-prone communities

In this study, we investigate the communication networks of urban, suburban, and rural communities from three US Midwest counties through a stochastic model that simulates the diffusion of information over time in disaster and in normal situations. To understand information diffusion in communities, we investigate the interplay of information that individuals get from online social networks, local news, government sources, mainstream media, and print media. We utilize survey data collected from target communities and create graphs of each community to quantify node-to-node and source-to-node interactions, as well as trust patterns. Monte Carlo simulation results show the average time it takes for information to propagate to 90% of the population for each community. We conclude that rural, suburban, and urban communities have different inherent properties promoting the varied flow of information. Also, information sources affect information spread differently, causing degradation of information speed if any source becomes unavailable. Finally, we provide insights on the optimal investments to improve disaster communication based on community features and contexts.

Effect of Domain Structure and Dielectric Interlayer on Switching Speed of Ferroelectric Hf0.5Zr0.5O2 Film

The nanosecond speed of information writing and reading is recognized as one of the main advantages of next-generation non-volatile ferroelectric memory based on hafnium oxide thin films. However, the kinetics of polarization switching in this material have a complex nature, and despite the high speed of internal switching, the real speed can deteriorate significantly due to various external reasons. In this work, we reveal that the domain structure and the dielectric layer formed at the electrode interface contribute significantly to the polarization switching speed of 10 nm thick Hf0.5Zr0.5O2 (HZO) film. The mechanism of speed degradation is related to the generation of charged defects in the film which accompany the formation of the interfacial dielectric layer during oxidization of the electrode. Such defects are pinning centers that prevent domain propagation upon polarization switching. To clarify this issue, we fabricate two types of similar W/HZO/TiN capacitor structures, differing only in the thickness of the electrode interlayer, and compare their ferroelectric (including local ferroelectric), dielectric, structural (including microstructural), chemical, and morphological properties, which are comprehensively investigated using several advanced techniques, in particular, hard X-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, energy dispersive X-ray spectroscopy, X-ray diffraction, and electron beam induced current technique.

An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change Memory

Write disturbance error (WDE) appears as a serious reliability problem preventing phase-change memory (PCM) from general commercialization, and therefore several studies have been proposed to mitigate WDEs. Verify-and-correction (VnC) eliminates WDEs by always verifying the data correctness on neighbors after programming, but incurs significant performance overhead. Encoding-based schemes mitigate WDEs by reducing the number of WDE-vulnerable data patterns; however, mitigation performance notably fluctuates with applications. Moreover, encoding-based schemes still rely on VnC-based schemes. Cache-based schemes lower WDEs by storing data in a write cache, but it requires several megabytes of SRAM to significantly mitigate WDEs. Despite the efforts of previous studies, these methods incur either significant performance or area overhead. Therefore, a new approach, which does not rely on VnC-based schemes or application data patterns, is highly necessary. Furthermore, the new approach should be transparent to processors (i.e., in-module), because the characteristic of WDEs is determined by manufacturers of PCM products. In this paper, we present an in-module disturbance barrier (IMDB) that mitigates WDEs on demand. IMDB includes a two-level hierarchy comprising two SRAM-based tables, whose entries are managed with a dedicated replacement policy that sufficiently utilizes the characteristics of WDEs. The naive implementation of the replacement policy requires hundreds of read ports on SRAM, which is infeasible in real hardware; hence, an approximate comparator is also designed. We also conduct a rigorous exploration of architecture parameters to obtain a cost-effective design. The proposed method significantly reduces WDEs without noticeable speed degradation or additional energy consumption compared to previous methods.

True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO.

Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO)exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobility degradation and high Schottky barriers at contacts, causing severe degradation of on-current and operation speed of the DRAM cells. Here, high-speed true nonvolatile DRAM cells are successfully demonstrated by deep suppression of doping density in the IGZO channel using in situ oxygen ion beam treatment and ohmic contact engineering by inserting a thin In-rich indium-tin-oxide (ITO) at contact regions. A record high on-current of 40µA µm-1 at a large positive threshold voltage of 1.78V enables the first true nonvolatile DRAM with the fastest write speed of 10ns and data retention up to 25 h under power interruption, five orders of magnitude higher than the previously projected values.

A Centralized Routing for Lifetime and Energy Optimization in WSNs Using Genetic Algorithm and Least-Square Policy Iteration

Q-learning has been primarily used as one of the reinforcement learning (RL) techniques to find the optimal routing path in wireless sensor networks (WSNs). However, for the centralized RL-based routing protocols with a large state space and action space, the baseline Q-learning used to implement these protocols suffers from degradation in the convergence speed, network lifetime, and network energy consumption due to the large number of learning episodes required to learn the optimal routing path. To overcome these limitations, an efficient model-free RL-based technique called Least-Square Policy Iteration (LSPI) is proposed to optimize the network lifetime and energy consumption in WSNs. The resulting designed protocol is a Centralized Routing Protocol for Lifetime and Energy Optimization with a Genetic Algorithm (GA) and LSPI (CRPLEOGALSPI). Simulation results show that the CRPLEOGALSPI has improved performance in network lifetime and energy consumption compared to an existing Centralized Routing Protocol for Lifetime Optimization with GA and Q-learning (CRPLOGARL). This is because the CRPLEOGALSPI chooses a routing path in a given state considering all the possible routing paths, and it is not sensitive to the learning rate. Moreover, while the CRPLOGARL evaluates the optimal policy from the Q-values, the CRPLEOGALSPI updates the Q-values based on the most updated information regarding the network dynamics using weighted functions.

Статический анализ на основе обобщённого абстрактного синтаксического дерева

The paper describes a unified representation for an abstract syntax tree (AST) suitable for static analysis of several programming languages. The proposed analysis scheme consists of saving an intermediate representation in the form of a unified AST from compilers of the corresponding languages and subsequent analysis of the saved trees. We have implemented this described representation for Java, Kotlin and Python. The unified AST analyzer has 27 checkers. In the paper we present structure and entities of our unified AST, provide more details regarding language specifics that have to be reflected in the UAST representation. We give extensive experimental results that show UAST generation and analysis speed, analysis quality, and comparison with the old scheme of analyzing compiler ASTs where applicable. As a result, we see that we observe some degradation of analysis speed, but we pay it for the separation of AST construction and checkers’ implementation. This separation allows easier support of many languages in the analyzer, where one can just generate UAST and support the required checker once within the UAST infrastructure instead of implementing a checker once per language.

(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories

Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs are integrated at the same advanced technology nodes as SRAMs [1]. In this talk, we will discuss the potential path for FEFET toward fulfilling this vision, by addressing the outstanding technological challenges: ultra-fast read-after write, reliability, voltage scaling and variation. To that end, our recent exposition on the trap and reliability physics of FEFETs will highlighted. We will highlight, based on newly developed experimental schemes, how the simultaneous capture and emission of electrons and holes in write cycles occur at the interface and the grain boundaries in the time domain, where in the band-diagram, these traps (acceptors and donors) are located and how exactly they result in the degradation of the read speed and reliability with continued write cycling. Based on these insights, we move on show how engineering the interfacial layer and the ferroelectric grain structure can enable ultra-fast read-after write and write voltage and dramatic improvements in reliability and variation, towards achieving a high-density, ultra-high speed memory technology.This research is supported by the National Science Foundation, the Defense Advanced Research Program Agency (DARPA), the Semiconductor Research Corporation (SRC) - Global Research Collaboration (GRC) program, the Applications and Systems-Driven Center for Energy-Efficient Integrated Nano Technologies (ASCENT), one of six centers in the Joint University Microelectronics Program (JUMP), a SRC program sponsored by the DARPA, and an Intel Rising Star award. [1] Mikolajick, T., Schroeder, U. & Slesazeck, S. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron Devices 67, 1434–1443 (2020).[2] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology." Nature Electronics 3.10 (2020): 588-597.

MDD: A Unified Model-Driven Design Framework for Embedded Control Software

Model-driven methods are widely used in embedded control software development. Current design tools, such as Ptolemy-II and Simulink, have strong modeling capability but their simulation and code generation functionalities are challenged by the increasing complexity of control requirements. For simulation, emulating the triggering of the actor leads to additional time overhead and speed degradation. For code generation, generating redundant content degrades the code quality. Besides, current tools do not have a unified interface, which makes it difficult to cooperation. In this article, we propose a unified model-driven design framework MDD to facilitate embedded control software development. MDD can support the unification of models built by different modeling tools for high-efficiency simulation and high-quality code generation. The MDD framework supports the expansion of more modeling tools, and also supports the expansion of more uses, such as unified testing and verification. First, it offers a model intermediate representation (MIR) and several corresponding parsers, which facilitate a unified representation and cooperation for different design tools. Then, based on data flow schedule analysis of the original MIR, intermediate code representation will be generated for optimized code synthesis. Finally, a variety of code translators will synthesize the intermediate code representation into the code of actual use, such as code for simulation and code for deployment. For evaluation, we enhance two widely used design tools in industry, Ptolemy-II and Simulink, and apply them on the implementation of several benchmark models and a real-world self-driving control software of our industrial collaborator. Using MDD can help reduce their simulation time by 98.9% and 92.6%, the generated code by 99.7% and 69.9% in the number of lines, and 94.3% and 34.3% in code execution time, respectively.

A Read Disturbance Tolerant Phase Change Memory System for CNN Inference Workloads

Phase-change memory (PCM) garners attention as the most promising nonvolatile memory (NVM). In particular, PCM is suitable for applications that are not memory intensive, and the convolutional neural network (CNN) inference is widely known as a representative computation-intensive model. Therefore, CNN inference seems to be very suitable for a PCM-based system. However, the PCM suffers from the characteristic of being vulnerable to disturbance errors. In particular, read disturbance error (RDE) becomes a serious problem for workloads involving a large number of zeros, and unfortunately, matrices in CNN are sparse, which inevitably incurs a significant amount of RDEs. In this paper, we present an RDE-tolerant PCM-based system for CNN inference workloads. The proposed method restores vulnerable data words by leveraging a dedicated SRAM-based table. Furthermore, we also propose a replacement policy, which detects non-urgent entries, by utilizing the contents (i.e., counters) in the table. As a result, the proposed method significantly reduces RDEs with minor speed degradation.

Analysis and control of a running spring-mass model with a trunk based on virtual pendulum concept

The spring-loaded inverted pendulum model has been one of the most studied conceptual models in the locomotion community. Even though it can adequately explain the center of mass trajectories of numerous legged animals, it remains insufficient in template-based control of complex robot platforms, being unable to capture additional dynamic characteristics of locomotion exhibited in additional degrees of freedom such as trunk pitch oscillations. In fact, analysis of trunk behavior during locomotion has been one of the motivations behind studying the virtual pivot point (VPP) concept, with biological inspiration and basis for both natural and synthetic systems with non-negligible trunk dynamics. This study first presents a comprehensive analysis of the VPP concept for planar running behaviors, followed by a systematic study of the existence and characteristics of periodic solutions. In particular, we investigate how periodic solutions depend on model control parameters and compare them based on stability and energetic cost. We then develop a feedback controller that can stabilize system dynamics around its periodic solutions and evaluate performance as compared to a previously introduced controller from the literature. We demonstrate the effectiveness of both controllers and find that the proposed control scheme creates larger basins of attraction with minor degradation in convergence speed. In conclusion, this study shows that the VPP concept, in conjunction with the proposed controller, could be beneficial in designing and controlling legged robots capable of running with non-trivial upper body dynamics. Our systematic analysis of periodic solutions arising from the use of the VPP concept is also an important step towards a more formal basis for comparisons of the VPP concept with bio-locomotion.

Multigrid reduction in time for non-linear hyperbolic equations

Time-parallel algorithms seek greater concurrency by decomposing the temporal domain of a partial differential equation, providing possibilities for accelerating the computation of its solution. While parallelisation in time has allowed remarkable speed-ups in applications involving parabolic equations, its effectiveness in the hyperbolic framework remains debatable: growth of instabilities and slow convergence are both strong issues in this case, which often negate most of the advantages from time-parallelisation. Here, we focus on the Multigrid Reduction in Time algorithm, investigating in detail its performance when applied to non-linear conservation laws with a variety of discretisation schemes. Specific attention is given to high-accuracy Weighted Essentially Non-Oscillatory reconstructions, coupled with Strong Stability Preserving integrators, which are often the discretisations of choice for such equations. A technique to improve the performance of MGRIT when applied to a low-order, more dissipative scheme is also outlined. This study aims at identifying the main causes for degradation in the convergence speed of the algorithm and finds the Courant-Friedrichs-Lewy limit to be the principal determining factor.

High-Speed Counter with Novel LFSR State Extension

This paper presents a high-speed counter architecture associated with novel LFSR state extension. By employing the proposed state extension, an <inline-formula><tex-math notation="LaTeX">$\emph {m}$</tex-math></inline-formula>-bit LFSR counter with <inline-formula><tex-math notation="LaTeX">$(\mathrm{2^{\mathit{m}}}-1)$</tex-math></inline-formula> states is modified to cover <inline-formula><tex-math notation="LaTeX">$\mathrm{2^{\mathit{m}}}$</tex-math></inline-formula> states without degrading the counting rate. Based on the property that only the low-order bits are frequently switched, the proposed counter consists of two sub-counters to achieve a high counting rate and reduce the hardware complexity needed to convert an LFSR state into a binary state. The low-order sub-counter is implemented with the proposed LFSR counter, and the high-order sub-counter is designed by employing the conventional synchronous binary counter. In addition, the implemented counter takes into account the speed degradation caused by the large fan-out of the high-order sub-counter. The proposed counter designed with standard cells operates at 2.08 GHz in a 65 nm CMOS technology, and its counting rate is almost independent of the counter size.

Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems.

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

Effects of compost, cover crops, and local conditions on degradation of two agricultural mulches in soil

AbstractBiobased and biodegradable mulches (BDM) are a potentially sustainable alternative to polyethylene plastic mulch because they can be tilled into the soil at the end of the growing season. However, their degradation rate in the soil is uncertain, limiting their on-farm adoption. The objective of this study was to determine whether organic soil management practices could be leveraged to speed degradation of two potentially BDM across two diverse agroecoregions [Lincoln (LNK) and Scottsbluff (SBF), NE, USA]. Management treatments included compost, compost extract, cover crops, all three of these practices combined and a control. The two mulch types studied were a nonwoven polylactic acid fabric with embedded wood particles (PLA), and a starch-polyester mulch film (BLK). Mulches were applied in spring 2017 for vegetable production and removed in fall after harvest. Recovered mulch was sectioned into squares 10 cm2and buried in mesh bags for 22 months. Mulch degradation, and soil chemical, physical and biological properties were measured at four times over 2 years. Management treatments applied seasonally across 2 years led to expected changes in soil properties, yet they had no effect on mulch degradation. Instead, mulch degradation was driven by the interaction of location and mulch type. The BLK mulch had degraded by 98% at LNK after 12 months, but only by half after 22 months at SBF. Degradation of PLA after 22 months was similar between locations with 29 ± 4% mulch mass remaining at SBF and 33 ± 4% remaining at LNK. Climate and soil characteristics at each location were strong determinants of mulch degradation. Specifically, soils at LNK were finer textured, lower in pH, higher in soil water content, organic matter and nitrates, and with greater bacterial abundance compared to SBF. The strong location by mulch type interaction observed could inform the development of regionally specific predictive models of degradation.

Fatigue characteristics of concrete subjected to indirect cyclic tensile loading: Insights from deformation behavior, acoustic emissions and ultrasonic wave propagation

This work aims to investigate the fatigue behaviour of concrete subjected to indirect cyclic tensile loading. A series of laboratory tests were performed based on Brazilian disk-shaped (BD) concrete samples. Two schemes of cyclic loading tests were designed by considering complex variations of maximum and minimum stresses. The effect of loading parameters, such as loading method, maximum and minimum stress, on sample deformation, acoustic emission (AE) characteristics, P-wave speed evolution and failure patterns were analysed. The features of AE behaviour and P-wave speed were compared between monotonic loading and indirect cyclic loading. Insight on the specific fatigue behaviour was obtained from AE hit counts, AE energy and P-wave speed degradation. The failure patterns of BD concrete samples are governed by the loading method as well as the stress paths. The stress paths have a direct and pronounced impact on the distribution of main and sub cracks on the surface of BD sample at failure.

Sequential routing framework: Fully capsule network-based speech recognition

Capsule networks (CapsNets) have recently gotten attention as a novel neural architecture. This paper presents the sequential routing framework which we believe is the first method to adapt a CapsNet-only structure to sequence-to-sequence recognition. Input sequences are capsulized then sliced by a window size. Each slice is classified to a label at the corresponding time through iterative routing mechanisms. Afterwards, losses are computed by connectionist temporal classification (CTC). During routing, the required number of parameters can be controlled by the window size regardless of the length of sequences by sharing learnable weights across the slices. We additionally propose a sequential dynamic routing algorithm to replace traditional dynamic routing. The proposed technique can minimize decoding speed degradation caused by the routing iterations since it can operate in a non-iterative manner without dropping accuracy. The method achieves a 1.1% lower word error rate at 16.9% on the Wall Street Journal corpus compared to bidirectional long short-term memory-based CTC networks. On the TIMIT corpus, it attains a 0.7% lower phone error rate at 17.5% compared to convolutional neural network-based CTC networks (Zhang et al., 2016).

Least Afflicted Load Balancing Algorithm (LALBA) for Performance Improvement of Multi-Scale Applications in Cloud Environment

Cloud computing is new image of Information Technology and the way applications are available to end-users. Also, the applications available are gaining popularity as being able to demonstrate the flexibility of use of resources as in Multi-Scale Cloud-Based Applications. These applications on the cloud are hosted on remote virtual machines with multi-tenancy architecture. Multi-tenant cloud computing architecture helps cloud users and customers to share computing resources and still the individual tenant's data is stored separately so as to make it is invisible to other tenants. With this multi-tenancy architecture, the application is being used by multiple people at the same time. Also, the application resides in various copies across various servers situated at different geographical locations. Virtual Machines that are housed in multiple Data Centers are coupled by way of load balancers. These load balancers are responsible for the optimal distribution of load/demand/tenant requests and the size of the data held within the request. So in short, two areas need to be focused on when architecting such systems. Firstly, the load must be balanced optimally across data centers and virtual machines for seamless operation at the back end. Secondly, at the front end, it is imperative that every tenant enjoys optimal service speeds without any degradation of service request speed. In case the back-end virtual machines are unbalanced in their load then there is bound to be degradation of services. For this very purpose, various researchers/academicians, and practitioners in the cloud space have been working tirelessly towards developing optimal algorithms to get the best load balancing architecture to ensure that the objective of seamless back end and front end quality of service in terms of average response times. Multi-Scale applications consist of variable payload for time and often unpredictable i.e. load can be increased/decreased suddenly or gradually. Hence to balance these loads equally at any time, a new algorithm is proposed. This algorithm considers the characteristics of multiscale applications in terms of data size and runtime characteristics of VM in terms of capacity and availability. Finally, the performance of this method is analyzed qualitatively as well as quantitatively by performing simulation experiments of multiscale applications.