Speculative Processing Research Articles

Checkpoint allocation and release

Out-of-order speculative processors need a bookkeeping method to recover from incorrect speculation. In recent years, several microarchitectures that employ checkpoints have been proposed, either extending the reorder buffer or entirely replacing it. This work presents an in-dept-study of checkpointing in checkpoint-based microarchitectures, from the desired content of a checkpoint, via implementation trade-offs, and to checkpoint allocation and release policies. A major contribution of the article is a novel adaptive checkpoint allocation policy that outperforms known policies. The adaptive policy controls checkpoint allocation according to dynamic events, such as second-level cache misses and rollback history. It achieves 6.8% and 2.2% speedup for the integer and floating point benchmarks, respectively, and does not require a branch confidence estimator. The results show that the proposed adaptive policy achieves most of the potential of an oracle policy whose performance improvement is 9.8% and 3.9% for the integer and floating point benchmarks, respectively. We exploit known techniques for saving leakage power by adapting and applying them to checkpoint-based microarchitectures. The proposed applications combine to reduce the leakage power of the register file to about one half of its original value.

Queuing algorithm for speculative Network Processors

This paper presents a queuing algorithm which is tailored for usage in speculative Network Processors (NPs). The queuing system uses Weighted-Fair Queuing queues (WFQ) which are extended by Priority Queues (PQ). While WFQ represents a common implementation in current routers supporting differentiated services, PQs allow to compensate extended protocol processing times due to mispredictions in a speculative system. When applying this concept, the generation of delay-jitter which would limit applicability of speculative packet processing for Real-Time (RT) traffic can be avoided. Utilising the presented queuing system in conjunction with speculative protocol processing in an NP, a latency reduction of up to 14.9% can be achieved compared to systems which support traditional packet processing methodologies.

Applying ELAN Strategies in Simulating Processors over Simple Architectures

The simulation of processors over simple architectures is important for enabling test and verification prior to the expensive implementation involved in the development of new hardware technologies. Arvind's group has illustrated how to describe processors by term rewriting systems and has introduced a technique for proving the correctness of specifications for elaborated processors with respect to basic ones. They propose that the described processors should be simulated over standard hardware description languages such as Verilog, after translating these rewrite descriptions adequately, and not directly over the rewriting specifications. In this work we show how rewriting-logic may be applied for purely rewriting based specification as well as simulation of processors. Furthermore, we show how rewriting based simulation may be used for evaluating the performance of important hardware aspects of processors. Rewriting-logic environments such as ELAN, the one we use here, are sufficiently versatile to allow for adequate specifications and simulations which through easy modifications of the strategies enable a dynamic verification of aspects intrinsically related to hardware properties such as the size and control of reorder buffers and the method of predictions used by speculative processors.

Evaluating the impact of reissued instructions on data speculative processor performance

In this paper, we investigate the impact of instructions reissued due to misspeculated data dependences on processor performance. Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level parallelism. When a misspeculation occurs, it is necessary to revert the processor state to a safe point where the speculation is initiated, with an instruction reissue mechanism utilized for that purpose. The instruction reissue suffers less miss penalties than instruction squashing which handles misspeculated control flows in current generation processors, but causes redundant instruction dispatching, i.e. multiple copies of an instruction are in flight in functional units. The effectiveness of data speculation would be diminished, if reissued instructions caused serious structural hazards. Therefore, we evaluate how the instruction reissue affects processor performance using an execution-driven simulator. We find that overhead due to instruction reissue is sufficiently small so as to allow data speculation to contribute to processor performance.

Using term rewriting systems to design and verify processors

Term rewriting systems (TRSs) offer a convenient way to describe parallel and asynchronous systems and prove an implementation's correctness with respect to a specification. TRS descriptions, augmented with proper information about the system building blocks, also hold the promise of high-level synthesis. High-level architectural descriptions that are both automatically synthesizable and verifiable would permit architectural exploration at a fraction of the time and cost required by current commercial tools. In this article, we use TRSs to describe a speculative processor capable of register renaming and out-of-order execution. We lack space to discuss a synthesis procedure from TRSs or to provide the details needed to make automatic synthesis feasible; Nevertheless, we show that our speculative processor produces the same set of behaviors as a simple nonpipelined implementation. Our descriptions of microarchitectures are more precise than those found in modern textbooks. The clarity of these descriptions lets us study the impact of features such as write buffers or caches, especially in multiprocessor systems.

Two-Dimensional Vlasov Simulation of Raman Scattering and Plasma Beatwave Acceleration on Parallel Computers

A two-dimensional relativistic Vlasov model for a multi-computer environment was developed to address the particle acceleration process in phase space, including situations relevant to forward Raman scattering (FRS) and plasma beatwave acceleration (PBWA). Attention was focused on its accuracy, stability, efficiency properties, and implementation facilities on massively parallel computers. The two-dimensional Vlasov code has been adapted to optimally use the particular parallel architecture of the T3D or T3E computer (both processor's specifications and node-to-node communications). Results obtained on a 64-node Cray T3D clearly show the details of particle acceleration in phase space, including very low density regions where particles-in-cell (PIC) codes simply run out of calculation particles. On the other hand optimization obtained on the T3D architecture leads to a CPU time of 9.5 μs per time step, per particle, per processor indicating that one processor on the Cray C94 computer is equivalent to 20 processors on the T3D computer. Finally, we note that the Vlasov code is able to achieve high parallel efficiency with scalability of order 2.