Specification Of Real-time Systems Research Articles

Specification and Verification of Multitask Real-Time Systems Using the OTS/CafeOBJ Method

Specification and Verification of Multitask Real-Time Systems Using the OTS/CafeOBJ Method

Exploring the ERTMS/ETCS full moving block specification: an experience with formal methods

Shift2Rail is a joint undertaking funded by the EU via its Horizon 2020 program and by main railway stakeholders. Several Shift2Rail projects aim to investigate the application of formal methods to new ERTMS/ETCS railway signalling systems that promise to move European railway forward by guaranteeing high capacity, low cost and improved reliability. We explore the ERTMS/ETCS level 3 full moving block specifications stemming from different Shift2Rail projects using Uppaal and statistical model checking. The results range from novel rigorously formalised requirements to an operational model formally verified against scenarios with multiple trains on a single railway line. From the gained experience, we have distilled future research goals to improve the formal specification and verification of real-time systems, and we discuss some barriers concerning a possible uptake of formal methods and tools in the railway industry.

Zone-based formal specification and timing analysis of real-time self-adaptive systems

Self-adaptive software systems are able to autonomously adapt their behavior at run-time to react to internal dynamics and to uncertain and changing environment conditions. Formal specification and verification of self-adaptive systems are tasks generally very difficult to carry out, especially when involving time constraints. In this case, in fact, the system correctness depends also on the time associated with events.

Model-based requirements specification of real-time systems with UML, SysML and MARTE

Activities of specification, analysis and design of real-time systems (RTS) are highly dependent on an effective understanding of the application domain and on the thorough representation of their basic requirements. Model-based approaches using modeling languages such as UML are often applied to contribute to handle complexity of RTS development. However, UML alone does not completely represent important features associated with these systems, such as relationship with hardware elements and an effective representation of timing constraints. This article explores the combined use of UML and its profiles SysML and MARTE for modeling hardware and software requirements of RTS, with application to a case of controlling urban road traffic. The SysML profile alone does not present the representation of temporal, behavioral and performance requirements. The MARTE profile provides key resources to specify non-functional requirements for RTS, in addition to a clear description of the various relevant aspects of requirements definition of RTS, as for instance, temporal aspects and constraints. The main objective is to present the combined application of SysML with MARTE stereotypes, which enables the specification of different features of individual software requirements. Thus, in addition to the factors mentioned above, we can say that the proposed approach has an important role to specify RTS at different levels of detail and levels of abstraction.

Multi approach for real-time systems specification: case study of GPU parallel systems

Specifying and modelling real-time systems (RTS) is not an easy task to do because there are many aspects to treat such as time constraints, scheduling and multi-tasking processing. Current RTS parallel applications deal with large amounts of data which require using devices such as GPUs. GPU is one of the main architectures that guaranties parallel execution. The specification of scheduling and timing on GPUs had always been a research problematic. UML/MARTE is an efficient semi-formal specification tool thanks to the UML's diagrams and MARTE's profiles. But it still none valid specification because it is not proved. That is why we propose to couple MARTE with the formal method Event B to have a valid specification and to validate the task scheduling on the GPU. A set of refinements had been proposed to cover the GPU specification and to generate an executable pre-code CUDA and OpenCL.

Action-level real-time DEVS modeling and simulation

For some classes of systems, it is advantageous to develop real-time models instead of step-wise or logical-time models. Toward this goal, the action-level real-time (ALRT) discrete-event system specification (DEVS) modeling and simulation approach is proposed. Modeling of actions is introduced into the parallel DEVS formalism using time invariants defined for real-time statecharts. Actions are specified in terms of time-windows that are to be executed in real-time. An abstract simulator protocol is devised for executing the ALRT-DEVS models under constrained computational resources. The approach is implemented in the parallel DEVS-Suite simulator. These models can be simulated on unitary computing platforms. A simple example switch model is detailed and tested to show the kinds of real-time modeling and simulation studies that can be supported.

Palmprint Recognition Based on Local Fisher Discriminant Analysis

A new palmprint recognition method based on local Fisher discriminant analysis(LFDA) is proposed. In order to solve the singularity of the eigenvalue equation matrix in small-size-sample cases such as image recognition, image down-sample is first used to reduce the palmprint space dimensionality. The LFDA is applied to extract the low projection vectors. Then the training images and test images are projected onto the projection vectors to get the local palmprint feature vectors. Finally, the cosine distance between two feature vectors is calculated to match palmprint. The new algorithm is tested in PolyU plmprint database. The results show that compared with principal component analysis (PCA), Fisher discriminant analysis (FDA), independent component analysis (ICA), and kernel principal component analysis (KPCA), the recognition rate of the new algorithm is the highest which is 98.95%, and the recognition time is 0.031s, so it meets the real-time system specification.

A survey on temporal logics for specifying and verifying real-time systems

Over the last two decades, there has been an extensive study of logical formalisms on specifying and verifying real-time systems. Temporal logics have been an important research subject within this direction. Although numerous logics have been introduced for formal specification of real-time and complex systems, an up to date survey of these logics does not exist in the literature. In this paper we analyse various temporal formalisms introduced for specification, including propositional/first-order linear temporal logics, branching temporal logics, interval temporal logics, real-time temporal logics and probabilistic temporal logics. We give decidability, axiomatizability, expressiveness, model checking results for each logic analysed. We also provide a comparison of features of the temporal logics discussed.

An Approach for Transforming LOTOS Specifications into MARTE Models

The transformation approaches and the traceability approaches from requirements specification to software architecture models are the hot topic, UML profile for MARTE (Modeling and Analysis of Real Time and Embedded systems) is proposed to model the software architectures of real-time and embedded systems, but MARTE models are inaccurate or ambiguous, because they are created based on natural language specifications. In order to obtain more accurate MARTE models, MARTE models need to be given formal semantics. In this paper we use LOTOS (Language of Temporal Ordering Specifications) to describe the requirements specification of real-time systems and propose an approach for generating MARTE models from LOTOS specifications by establishing a mechanism for transforming LOTOS specifications into MARTE models, the MARTE models generated by this approach can increase the reliability for designing the software architectures of real-time systems.

The Formal Design Models of Digraph Architectures and Behaviors

Graphs are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. Problems in sciences and engineering can be formulated and solved by the graph model. This paper develops a comprehensive design pattern of formal digraphs using the Doubly-Linked List (DLL) architecture. The most complicated form of graphs known as the weighted digraph is selected as a general graph model, based on it simple graphs such as nondirected and/or nonweighted ones can be easily derived and tailored. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of digraphs to be rigorously designed and implemented in a top-down approach. The architectural models of digraphs are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of digraphs is implemented using nodes of DLL dynamically created in the memory. The behavioral models of digraphs are specified and refined by a set of 18 Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node manipulation operations. This work has been applied in a number of real-time and nonreal-time system designs and specifications such as a Real-Time Operating System (RTOS+), graph-based and tree-based applications, and the ADT library for an RTPA-based automatic code generation tool.

Some issues in real-time systems verification using time Petri Nets

Time Petri Net (TPN) models have been widely used to the specification and verification of real-time systems. However, the claim that most of these techniques are useful for real-time system verification can be discussed, based on two assumptions: i) to be suitable for real-time systems verification, a technique must be able to check timing properties, both safe and behavioral, and ii) the underlying algorithm must be efficient enough to be applied to complex systems design. In this paper we will discuss the suitability of commonly accepted verification techniques that use model-checking as a verification framework and TPN as a description model. We present a new algorithmic approach that allows computation of end-to-end time between activities over an abstract state space model. The proposed approach needs to compute the abstract state space only once improving the efficiency of the verification process and turning it suitable for large problems. We also introduce a new sufficient condition for abstract states space to preserve the branching time properties that yields more compact graphs than the condition already used in actual approaches. The approach would fit a design environment also based on Petri Nets called GHENeSys (General Hierarchical Enhanced Petri Nets). The results obtained, using our verification approach are compared with similar available approaches.

Compositional specification of real time embedded systems by priority time Petri Nets

An important key challenge in Embedded Real Time Systems (ERTS) analysis is to provide a seamless scheduling strategy. Formal methods for checking the temporal characteristics and timing constraints at a high abstraction level have proven to be useful for making the development process reliable. In this paper, we present a Petri Net modeling formalism and an analysis technique which supports not only systems scheduling analysis but also the compositional specification of real time systems. The proposed Priority Time Petri Net gives determinism aspect to the model and accelerates its execution. Indeed, a compositional specification of a PTPN for complex application and multiprocessor architecture that solves the problem of hierarchy is presented.

Method for Generating Software Architecture Models from Formal Specifications

This paper uses LOTOS to describe the requirement specification of real-time systems and proposes a method for generating software model from formal specifications by establishing a mechanism that translates LOTOS specifications into UML-RT models.Finally,this paper illustrates how to use the method when modeling real-time software.The UML-RT models generated by this method can increase the reliability for designing the software for real-time systems.

Specification and verification of real-time systems using POLA

Real-time systems are becoming more and more complex, making it hard for the industrial community to actually use experimental tools which are able to resolve some of the specification and verification issues of such systems. This work presents a tool which automatically transforms a domain specific language for the specification of real-time systems into its corresponding time Petri net semantics together with some related logical formulas. Consequently, the validity of the generated formulas are automatically checked with regard to the generated model using the TINA model checking toolbox. Using this automatic tool chain, the users can check the validity of real-time systems without any prerequisite knowledge of how it actually was accomplished.

Timed Modal Logics for Real-Time Systems

In this paper, a timed modal logic L c is presented for the specification and verification of real-time systems. Several important results for L c are discussed. First we address the model checking problem and we show that it is an EXPTIME-complete problem. Secondly we consider expressiveness and we explain how to express strong timed bisimilarity and how to build characteristic formulas for timed automata. We also propose a compositional algorithm for L c model checking. Finally we consider several control problems for which L c can be used to check controllability.

Efficient Verification and Optimization of Real-Time Logic-Specified Systems

Embedded and real-time systems are increasingly common and complex, requiring formal specification and verification in order to guarantee their satisfaction of desirable safety and timing requirements. Real-Time Logic (RTL) has been used to capture both the specification (denoted by SP) of a real-time system and the desirable safety assertions (denoted by SA) with respect to this system specification. A verification procedure then determines whether the safety assertions hold with respect to the system specification. However, the satisfiability problem for RTL (i.e., "Can SP \rightarrow SA hold?”), as well as for other first order logics, is undecidable. Consequently, efforts have been focused on identifying nontrivial classes of formulas sufficiently practical for describing industrial real-time systems for which the verification and debugging can be done via efficient heuristics. One such class of formulas is the so-called path RTL. The first contribution of this paper is to extend the existing path RTL class without sacrificing the time complexity of the traditional path RTL heuristic for verification. This implies that we can specify and verify real-time systems, which we were unable to do using the existing path RTL, in the extended path RTL. For real-time systems with large specifications, there is a lot of room for improvement in the algorithms used for verification and debugging. The second contribution of this paper is an efficient method to perform verification and debugging of real-time systems specifications using decomposition techniques. Our idea is to decompose the constraint graph, used in existing approaches, into independent subgraphs so that it is no longer necessary to analyze the entire specification at once, but rather its individual and smaller components. However, none of the above heuristics necessarily finds an “optimal implication.” After verifying SP \rightarrow SA and deploying the system implementing SP, performance changes as a result of power saving, faulty components, and cost saving in the processing platform for the tasks specified in SP affect the computation times of the specified tasks. This leads to a different but related SP, which would violate the original SP \rightarrow SA theorem if SA remains the same. It is desirable, therefore, to determine an optimal SP with the slowest possible computation times for its tasks such that the SA is still guaranteed. This is clearly a fundamental issue in the design and implementation of highly dependable real-time/embedded systems. The third contribution of this paper tackles this fundamental issue by describing a new method for relaxing SP and tightening SA such that SP \rightarrow SA is still a theorem. We have implemented this method in the Java-based DEVO-RTL tool and tested it on several industrial real-time systems. Experimental results show that only about 10 percent of the running time of the heuristic for the verification of SP \rightarrow SA is needed to find an optimal theorem.

A process algebraic framework for specification and validation of real-time systems

Abstract Following the trend to combine techniques to cover several facets of the development of modern systems, an integration of Z and CSP, called Circus , has been proposed as a refinement language; its relational model, based on the unifying theories of programming (UTP), justifies refinement in the context of both Z and CSP. In this paper, we introduce Circus Time , a timed extension of Circus , and present a new UTP time theory, which we use to give semantics to Circus Time and to validate some of its laws. In addition, we provide a framework for validation of timed programs based on FDR, the CSP model-checker. In this technique, a syntactic transformation strategy is used to split a timed program into two parallel components: an untimed program that uses timer events, and a collection of timers. We show that, with the timer events, it is possible to reason about time properties in the untimed language, and so, using FDR. Soundness is established using a Galois connection between the untimed UTP theory of Circus (and CSP) and our time theory.

Comments on temporal logics for real-time system specification

The article “Temporal Logics for Real-Time System Specification” surveys some of the relevant literature dealing with the use of temporal logics for the specification of real-time systems. Unfortunately, it introduces some imprecisions that might create some confusion in the reader. While a certain degree of informality is certainly useful when addressing a broad audience, imprecisions can negatively impact the legibility of the exposition. We clarify some of its remarks on a few topics, in an effort to contribute to the usefulness of the survey for the reader.

Validating software requirements with enactable use case descriptions

Use cases have gained wide acceptance since the standardisation of the UML by the Object Management Group in 1997. This paper addresses the inadequacy of use cases for expressing intra-use case and inter-use case dependencies. We present a state-based approach for facilitating explicit consideration of such dependencies in use case descriptions, and a support tool is described, which provides enaction of the state-based use cases to support validation. We outline an industrial study involving the specification of real-time monitoring systems, wherein we demonstrate that enaction of the state-based use cases highlighted important dependency issues that had not been revealed within standard use cases.

Timed Automata Patterns

Timed automata have proven to be useful for specification and verification of real-time systems. System design using timed automata relies on explicit manipulation of clock variables. A number of automated analyzers for timed automata have been developed. However, timed automata lack composable patterns for high-level system design. Specification languages like Timed Communicating Sequential Process (CSP) and Timed Communicating Object-Z (TCOZ) are well suited for presenting compositional models of complex real-time systems. In this work, we define a set of composable Timed Automata patterns based on hierarchical constructs in time-enriched process algebras. The patterns facilitate the hierarchical design of complex systems using timed automata. They also allow a systematic translation from Timed CSP/TCOZ models to timed automata so that analyzers for timed automata can be used to reason about TCOZ models. A prototype has been developed to support system design using timed automata patterns or, if given a TCOZ specification, to automate the translation from TCOZ to timed automata.