Specification Description Language Research Articles

A Custom Parallel Hardware Architecture of Nonlinear Model-Predictive Control on FPGA

This article presents the field-programmable gate array (FPGA) implementation of a particle swarm optimization (PSO)-based nonlinear model-predictive control (NMPC) for applications with millisecond timescales and resource-constrained embedded systems. A custom hardware circuit architecture of an NMPC controller, which mainly includes phase-locked loop clock, universal asynchronous receiver transmitter interface, trigonometric function, random number generator, objective function, and PSO solver modules, is implemented on the FPGA based on a hardware description language specification. It employs parallelism, pipelining, and specialized numerical formats to enhance the online computation performance of NMPC. In addition, the partial parallel expansion calculations of the fitness (objective) function and the particle position update are adopted for trading off the computational performance against resource usage. The hardware-in-the-loop experimental results through controlling a wheeled mobile robot model demonstrate that the design is capable of computing the required control action in real time by using a midrange FPGA, while still offering good control performance.

End-User Composition of Graphical User Interfaces for PalCom Systems

In ubiquitous computing, end-user composition allows users to combine multiple single-purpose devices into new, interesting constellations. In PalCom – a ubiquitous middleware – this is achieved without the need to write program code. In this paper we present a solution that in the same way allows users to create Graphical User Interfaces (GUIs) for such systems without coding. The approach is to focus on presenting functionality in a GUI rather than attaching functionality to manually added components. We see this as an inverted way of working with GUI development. The solution was realized in the form of a graphical editor for a PalCom specific User Interface Description Language. The tool produces platform independent GUI descriptions that can be interpreted on any platform. When compared to another common tool, the presented editor exhibited roughly 10x shorter development times. The learning time for new users was also evaluated with positive outcome, and a scalability evaluation showed that the solution can be used to create professional grade GUIs.

Prototype of a Decision Table Generation Tool from the Formal Specification

This research has implemented a prototype of a decision table generation tool from the specification (the formal specification) described in a formal specification language. This paper uses the formal specification description language VDM++ which is the lightweight formal methods VDM (Vienna Development Method) to write the formal specification. We applied some general specifications to the prototype, in order to evaluate its usefulness. As a result, the prototype has improved the efficiency in test design with formal methods.

ISemServ: A model-driven approach for developing semantic web services

The benefits of incorporating Semantic Web Services in web applications are well documented. However, both the real-world implementation and adoption of these services are still rather limited in practice. This is despite the promises that extend syntactic Web services with capabilities such as automatic service discovery, composition, and execution. Some of the barriers to the real-world implementation are the complexities and tool support related to the development of Semantic Web Services. In this article, the main challenge that is addressed is the tight coupling of existing Semantic Web Services (SWS) development platforms to specific semantic description languages and service description languages, which unintentionally lead to unbending service development environments. The main contribution in this article is therefore a model-driven approach called iSemServ that exploits mature technologies, such as UML, and model-transformation techniques for simplifying and semi-automating the development of SWS using description languages of choice, such as Web Ontology Language for Services (OWL-S) and Web Application Description Language (WADL). A design science research methodology was employed in conducting the study. The suggested approach was practically implemented as an Eclipse plug-in and evaluated based on a real-world use case scenario and comparative analysis of related solutions. The evaluation results show that our proposed solution is relevant and appropriate in aiding the semi-automatic development of SWS, albeit with a number of limitations that could be addressed by extending the proposed practical solution.

Performance-Driven Clustering of Asynchronous Circuits

This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput and latency constraints, and minimizing area. This method provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original Register-Transfer Level (RTL) specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.

An architectural approach to the analysis, verification and validation of software intensive embedded systems

EAST-ADL is a domain specific Architecture Description Language (ADL) for safety-critical and software-intensive embedded systems. The language allows a formalized and traceable description of a wide range of engineering concerns throughout the entire lifecycle of system development. This makes it possible to fully utilize the leverage of state-of-the-art methods and tools for the development of correct-by-construction system functions and components in a seamless and cost efficient way. This paper focuses on the recent advancement of EAST-ADL in supporting an architecture-centric analysis, verification&validation of complex behaviors for the purposes of requirements engineering, application design, and safety engineering. The approach is architecture centric because all behavior descriptions are formalized and connected to a set of standardized design artifacts sitting at multiple levels of abstractions. We present the language design to support this, the theoretical underpinning and tool implementation. To show the capability of EAST-ADL, we also introduce an algorithm and its implementation for transforming the EAST-ADL behavior models to SPIN models for logic model checking. Exploiting mature state-of-the-art technologies from computer science, electronic engineering, and other related domains for a model-based incremental system development, the contribution enables the developers of embedded systems and software to maintain various engineering concerns coherently using EAST-ADL.

ASDeX: a formal specification for analog circuit enabling a full automated design validation

In this paper an XML based language format to describe specifications of analog IPs and its usage in a validation flow is presented. With the help of an XML-Schema-Definition (XSD) a specification description language called Analog Specification Description in XML (ASDeX) is introduced. An ASDeX-file contains not only specification parameters but also measurement definitions and testbenches to enable specification validation based on simulation. The intention is to generate executable modules (tasks) for running simulations and extracting and checking the actual property values of analog circuits. The task generation is based on a generic template approach using a Meta-Simulator to achieve vendor independent analog IP representation including IP verification.

Algorithm for Web Service Discovery Based on Information Retrieval Using WordNet and Linear Discriminant Functions

An algorithm based on information retrieval that applies the lexical database WordNet together with a linear discriminant function is proposed. It calculates the degree of similarity between words and their relative importance to support the development of distributed applications based on web services. The algorithm uses the semantic information contained in the Web Service Description Language specifications and ranks web services based on their similarity to the one the developer is searching for. It is applied to a set of 48 real web services in five categories, then compared them to four other algorithms based on information retrieval, showing an averaged improvement over all data between 0.6% and 1.9% in precision and 0.7% and 3.1% in recall for the top 15 ranked web services. The objective was to reduce the burden and time spent searching web services during the development of distributed applications, and it can be used as an alternative to current web service discovery systems such as brokers in the Universal Description, Discovery, and Integration (UDDI) platform.

FIESTA: A GENERIC FRAMEWORK FOR INTEGRATING NEW FUNCTIONALITIES INTO SOFTWARE ARCHITECTURES

When an application must evolve to cope with new context and user requirements, integrating new functionalities into its software architecture is necessary. The architect has thus to manually modify the architecture description, which is often tedious and error prone. In this paper, we propose FIESTA, a generic framework for automatically integrating new functionalities into an architecture description. Our approach is inspired by TranSAT, an integration framework. However, TranSAT is dedicated to a specific architecture description language (ADL) while our approach is ADL-independent. We have performed a domain analysis, studying for many ADLs how to integrate new functionalities. Based on this analysis, we have defined a generic ADL model to manipulate and reason about architectural elements that are involved in integration. Furthermore, we have developed a generic integration engine.

Direct Model Checking Matrix Algorithm

During the last decade, Model Checking has proven its efficacy and power in circuit design, network protocol analysis and bug hunting. Recent research on automatic verification has shown that no single model-checking technique has the edge over all others in all application areas. So, it is very difficult to determine which technique is the most suitable for a given model. It is thus sensible to apply different techniques to the same model. However, this is a very tedious and time-consuming task, for each algorithm uses its own description language. Applying Model Checking in software design and verification has been proved very difficult. Software architectures (SA) are engineering artifacts that provide high-level and abstract descriptions of complex software systems. In this paper a Direct Model Checking (DMC) method based on Kripke Structure and Matrix Algorithm is provided. Combined and integrated with domain specific software architecture description languages (ADLs), DMC can be used for computing consistency and other critical properties.

HPC‐Europa single point of access as a framework for building science gateways

AbstractOne of the goals of the HPC‐Europa project is to provide users with a single point of access (SPA) to the resources of HPC centers in Europe. To this end, the HPC‐Europa portal is being built to provide transparent, uniform, flexible and intuitive user access to HPC‐Europa resources. This portal will hide the underlying complexity and heterogeneity of these resources and the services that provide access to them. Since the computational environment of HPC‐Europa is strongly heterogeneous, even in terms of the deployed Grid middleware, we need a mechanism that maps a uniform graphical user interface to the functionality provided by services available in the institutions belonging to the HPC‐Europa consortium. In addition, accounting information has to be stored and provided on demand for both limiting resource usage and charging purposes in the HPC‐Europa infrastructure. The important goal of the SPA is also to provide the means to support user access to specific applications. This should make access to Grid infrastructures easier for end‐users. Both mechanisms (generic and application‐specific interfaces), along with additional tools, will combine to provide flexible and efficient software for building science gateways for researchers in various domains. In this paper, we describe the architecture of the SPA, which is based on the GridSphere portal framework. We present a mechanism for enabling end‐users to transparently access services available in the HPC‐Europa environment. The uniform job submission interface that uses this mechanism and is based on the Job Specification Description Language (JSDL) is presented. The mechanism supporting development of application‐specific user interfaces is also described. Finally, we discuss relevant issues and interoperability problems connected with the development of the SPA, in particular those concerning job submission, security and accounting. Copyright © 2006 John Wiley & Sons, Ltd.

A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems

In this paper we present a methodology for optimizing complex datapath oriented digital circuits. An optimizer was developed based on the earlier development of an automatic circuit synthesizer that synthesizes hardware description language specifications based on available functional modules. A genetic algorithm is tailored to the problem of digital circuit optimization through the development of specific structures and procedures. In particular, a concise encoding of the circuit is developed that the genetic algorithm can manipulate. Specific crossover and mutation mechanisms are also developed to complement the functionality of the synthesizer. The searches are effected by altering module data type, hardware resource sharing, and module implementation version. A fitness function is derived that makes use of a number of optimization parameters to objectively evaluate each particular circuit. The features of each circuit are calculated and estimated during the analysis phase.

Swiss cadastral core data model—experiences of the last 15 years

In Switzerland, the need for a standardized data model and exchange format for cadastral data has already been expressed in 1987. The requirement for a clearly defined data model that can be adapted in flexible ways lead to the concept of a specific data description language, with which the whole cadastral core data model was defined. The data description language was named INTERLIS, while the data model for cadastral surveying became known as AV93, enacted in 1993 with a Federal ordinance. The requirements for the core data model as well as the data description language evolved since INTERLIS has been complemented and became INTERLIS2 in 2003. In 2004, a new revised core data model has been adopted, taking many of the discovered drawbacks into account. The revised core data model was named DM.01. The concept of the data description language INTERLIS is very similar to the GML/XML concept that is in full development on the international level. This paper describes the experiences made with INTERLIS and the cadastral core data model in Switzerland over the last 15 years with the perspective of possible lessons learnt that might support international developments. The paper also includes two case studies—cadastral surveying and interface with land registration—illustrating the practical applications.

An “abstract process” approach to algebraic dynamic architecture description

Current software development methodologies recognize the critical importance of the architectural concerns during the design phase. Software Architecture promises to be the solution for a number of recurring problems; but to do so, the first task is to be able to obtain a precise description of a system architecture. In late years, a number of specific architecture description languages (A dls) have been proposed in order to achieve the required precision. Most of them have solid formal foundations; among them, several process-algebraic A dls stand out for their popularity and expressive power. The algebraic approach to architecture description is probably the most successful in the field. There is a natural intuition relating the concepts of algebraic process and architectural component; anyway, none of the existing approaches seems to have found the right balance between them. This article explains what is the problem with them, and defines the informal concept of abstract process, trying to provide a reference for the right level of abstraction. After presenting the concept, the article presents a dynamic, reflective A dl named P i L ar, which has been designed using this notion. The syntax and semantics of this language are briefly summarized and explained. Finally, the classic example of the Gas Station is described in terms of P i L ar, and then compared to previous presentations in other A dls.

The PROFIBUS formal specification: a comparison between two FDTs

Formal description languages, like ESTELLE [7], Language Temporary Of Ordering Specification (LOTOS) [8] or Specification Description Language (SDL) [9], allow us to specify complex system requirements in an ambiguities free and complete way [26]. The choice of what formal language to use in a particular system specification must be taken a priori by the system designer [5]. It would be useful to have comparative information about systems described with some of these languages, to know which one would fit better to that system. The literature published on this topic [1,14,22] compares too simple systems. This paper deals with this aspect and compares the formal specification of the PROcess FIeld BUS (PROFIBUS) communications protocol in both languages LOTOS and SDL.

Configuration and evaluation of an emulator for telecommunication service specification including screening service

There is a need for technologies that can rapidly and accurately acquire the request specifications for telecommunication services and that can mechanically support specification verification in the upper-level process of the upstream processes of telecommunication service software development. In this paper, we propose an emulator for telecommunication service specifications that supports improved understanding of a specification's operation by testing the operation based on the telecommunication service specification described by state transition rules (STRs), which constitute a declarative telecommunication service specification description language, and can verify the validity of the telecommunication service specification and check for contention between multiple services. Specifically, network functions and terminal functions are set up in multiple work stations connected over a LAN. The service scenario described by the STRs is saved on the network function side. Then based on the scenario, the operations are executed sequentially. We propose a system extension method corresponding to a screening service that selects a service provided with specific conditions in a customized service that is specified to match the user's preferences. This extension makes available an emulator of the comprehensive telecommunication service specifications, which include the screening conditions specified by the user. Thus, further improvement in the user's satisfaction with the requests in the telecommunication service specification can be expected. The effectiveness of the system configured on the LAN was evaluated. © 2000 Scripta Technica, Electron Comm Jpn Pt 1, 84(4): 11–21, 2001

Hardware evolution — a real “life on the silicon”

A hardware evolutionary system is proposed that automatically changes hardware description language specifications of digital circuits and adapts them to applied specific problems. Outputs from the system can be converted to real electronic circuits instead of the conceptual data structure in computer memory. Such individual circuits can be seen as an artificial life that behaves at electronic speed: true “life on the silicon.”

Specification description language and program synthesis for ECU software Yutaka Inamori, Kin-ichi Wada, Shigeharu Teshima (Toyota Central Research & Development Laboratories, Inc.)

Specification description language and program synthesis for ECU software Yutaka Inamori, Kin-ichi Wada, Shigeharu Teshima (Toyota Central Research & Development Laboratories, Inc.)

A language to describe the growth of neurites.

How can biological plasticity been added to a simulation of neuritic growth? Coming from this question, we have chosen a new access to simulate neuritic growth under the very aspect of meaningful and progredient development of single cells. Based on a specific description-language, we have set up a computer-program, to construct neurite-models and to simulate neuritic interaction during their development. Instead of using mathematical equations, we define various types of cytoskeletons by taking a specified graph grammar. Using this technique, we are able to define strings, combined with other influencing parameters, which allow the setting up of very naturally behaving artificial nervecells, in which distinct statistical variance and fixed rules as given in DNA operate together. In this paper, we want to discuss the underlying principles of the given grammar and to show some results from these computer-simulations, which enable us to study growth, development and other specific characteristics of neurites within a simulator in comparison to in vivo-experiments.

Handling Real-Time communication constraints in a mobile station used for the pan European digital mobile communication network

This paper provides some insight of the communication mechanism for the protocol handling in a mobile station (MS) being used for the pan European digital mobile network. SDL (Specification Description Language) is used as a means of facilitating the specification as well as for the development of the protocol stack for a MS. Emphasis is put on the employed Real Time interprocess communication mechanism necessary to meet time constraints imposed by the application. An example is given to discuss the properties of the employed SDL based Real-Time System in more detail.