Special-purpose Architectures Research Articles

The geophysics of community, place, and identity in the Mississippian Illinois River Valley

Recent geophysical surveys at six sites in the Illinois River Valley (IRV), just north of the Greater Cahokia area, provide new insights into the region’s volatile era of Mississippian occupation by revealing a series of important changes in community organization that occurred from the eleventh to fifteenth centuries. Geophysical data allow us to evaluate these changes through the lens of site layout, special-purpose architecture and communal space, and the spatial alignment of site features to consider how the construction of Mississippian spaces structured social organization and identities. When considered in conjunction with data from previous excavations in the region, this geophysical work indicates that religion played a key role in forging new relationships and shared identities among early Mississippian IRV and Cahokian groups. Our analysis also reveals that IRV Mississippians reconfigured important aspects of these religious practices and socio-political relationships in the context of warfare-induced population nucleation beginning around 1200 CE, leading to more locally structured identities over time.

Introduction Of Special Issue on FPGA-Based Computing [From The Guest Editors

The articles in this special section focus on field-programmable gate arrays (FPGAs)- based computing. Over the past three decades, FPGAs have evolved from small chips with a few thousand logic blocks to billion- transistor system-on-chips. Modern FPGAs provide massive fine-grained parallelism, high energy efficiency, and more predictable performance than CPUs and GPUs. More importantly, they can be reconfigured to implement a special-purpose architecture that is specifically customized based on the key characteristics of a target application (or domain). For these reasons, recent years have seen a rapidly increasing use of FPGAs for computing, where a plethora of new architectures, compilers, and FPGA-accelerated applications are being demonstrated and actively developed. This special issue includes five survey papers from renowned experts in the field of FPGAs. The goal is to summarize some of the recent advances on FPGA-based computing, to elucidate the architecture- and application-level trends, and to promote new tools to enable productive FPGA programming.

Algorithmic Skeletons and Parallel Design Patterns in Mainstream Parallel Programming

This paper discusses the impact of structured parallel programming methodologies in state-of-the-art industrial and research parallel programming frameworks. We first recap the main ideas underpinning structured parallel programming models and then present the concepts of algorithmic skeletons and parallel design patterns. We then discuss how such concepts have permeated the wider parallel programming community. Finally, we give our personal overview—as researchers active for more than two decades in the parallel programming models and frameworks area—of the process that led to the adoption of these concepts in state-of-the-art industrial and research parallel programming frameworks, and the perspectives they open in relation to the exploitation of forthcoming massively-parallel (both general and special-purpose) architectures.

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM

The wide adoption of deep neural networks has been accompanied by ever-increasing energy and performance demands due to the expensive nature of training them. Numerous special-purpose architectures have been proposed to accelerate training: both digital and hybrid digital-analog using resistive RAM (ReRAM) crossbars. ReRAM-based accelerators have demonstrated the effectiveness of ReRAM crossbars at performing matrix-vector multiplication operations that are prevalent in training. However, they still suffer from inefficiency due to the use of serial reads and writes for performing the weight gradient and update step. A few works have demonstrated the possibility of performing outer products in crossbars, which can be used to realize the weight gradient and update step without the use of serial reads and writes. However, these works have been limited to low precision operations which are not sufficient for typical training workloads. Moreover, they have been confined to a limited set of training algorithms for fully-connected layers only. To address these limitations, we propose a bit-slicing technique for enhancing the precision of ReRAM-based outer products, which is substantially different from bit-slicing for matrix-vector multiplication only. We incorporate this technique into a crossbar architecture with three variants catered to different training algorithms. To evaluate our design on different types of layers in neural networks (fully-connected, convolutional, etc.) and training algorithms, we develop PANTHER, an ISA-programmable training accelerator with compiler support. Our design can also be integrated into other accelerators in the literature to enhance their efficiency. Our evaluation shows that PANTHER achieves up to 8.02×, 54.21×, and 103× energy reductions as well as 7.16×, 4.02×, and 16× execution time reductions compared to digital accelerators, ReRAM-based accelerators, and GPUs, respectively.

A survey on applications and architectural-optimizations of Micron’s Automata Processor

Abstract Problems from a wide variety of application domains can be modeled as “nondeterministic finite automaton” (NFA) and hence, efficient execution of NFAs can improve the performance of several key applications. However, traditional architectures, such as CPU and GPU are not inherently suited for executing NFAs, and hence, special-purpose architectures are required for accelerating them. Micron’s automata processor (AP) exploits massively parallel in-memory processing capability of DRAM for executing NFAs and hence, it can provide orders of magnitude performance improvement compared to traditional architectures. In this paper, we present a survey of techniques that propose architectural optimizations to AP and use it for accelerating problems from various application domains. This paper will be useful not only for computer architects and processor-designers, but also for researchers in the field of bioinformatics, data-mining, machine learning and others.

A Survey of Paradigms for Building and Designing Parallel Computing Machines

In this paper we describe paradigms for building and designing parallel computing machines. Firstly we elaborate the uniqueness of MIMD model for the execution of diverse applications. Then we compare the General Purpose Architecture of Parallel Computers with Special Purpose Architecture of Parallel Computers in terms of cost, throughput and efficiency. Then we describe how Parallel Computer Architecture employs parallelism and concurrency through pipelining. Since Pipelining improves the performance of a machine by dividing an instruction into a number of stages, therefore we describe how the performance of a vector processor is enhanced by employing multi pipelining among its processing elements. Also we have elaborated the RISC architecture and Pipelining in RISC machines After comparing RISC computers with CISC computers we observe that although the high speed of RISC computers is very desirable but the significance of speed of a computer is dependent on implementation strategies. Only CPU clock speed is not the only parameter to move the system software from CISC to RISC computers but the other parameters should also be considered like instruction size or format, addressing modes, complexity of instructions and machine cycles required by instructions. Considering all parameters will give performance gain . We discuss Multiprocessor and Data Flow Machines in a concise manner. Then we discuss three SIMD (Single Instruction stream Multiple Data stream) machines which are DEC/MasPar MP-1, Systolic Processors and Wavefront array Processors. The DEC/MasPar MP-1 is a massively parallel SIMD array processor. A wide variety of number representations and arithmetic systems for computers can be implemented easily on the DEC/MasPar MP-1 system. The principal advantages of using such 64×64 SIMD array of 4-bit processors for the implementation of a computer arithmetic laboratory arise out of its flexibility. After comparison of Systolic Processors with Wave front Processors we found that both of the Systolic Processors and Wave front Processors are fast and implemented in VLSI. The major drawback of Systolic Processors is the problem of availability of inputs when clock ticks because of propagation delays in connection buses. The Wave front Processors combine the Systolic Processor architecture with Data Flow machine architecture. Although the Wave front processors use asynchronous data flow computing structure, the timing in the interconnection buses, at input and at output is not problematic..

Behavioral architecture of the cortical sheet

Summary The effortless ability of vertebrates to explore and exploit their environment is strongly correlated with the evolution of the most anterior part of their nervous system, the forebrain, where data from autonomic (visceral), limbic (emotive), and internal and peripheral sensors of the external world are combined to develop, decide, and deploy advantageous behaviors. The correlation of behavioral performance with forebrain expansion suggests that evolution has discovered the developmental means of building vertebrate brains to produce a scalable, special-purpose architecture for efficiently processing and expressing behavior. In mammals, the exuberant expansion of this forebrain is dominated by the growth of their cortex — the two-dimensional sheet that is the major source of their intelligent behavior, especially for primates.

A Special-Purpose Architecture for Solving the Breakpoint Median Problem

In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005times over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417times. The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based on complex, control-dependent combinatorial optimization.

A neural network approach for credit risk evaluation

The Basel Committee on Banking Supervision proposes a capital adequacy framework that allows banks to calculate capital requirement for their banking books using internal assessments of key risk drivers. Hence the need for systems to assess credit risk. Among the new methods, artificial neural networks have shown promising results. In this work, we describe the case of a successful application of neural networks to credit risk assessment. We developed two neural network systems, one with a standard feedforward network, while the other with a special purpose architecture. The application is tested on real-world data, related to Italian small businesses. We show that neural networks can be very successful in learning and estimating the in bonis/ default tendency of a borrower, provided that careful data analysis, data pre-processing and training are performed.

VLSI Algorithms and architectures for JPEG2000

In this paper, we presented VLSI algorithms and architectures for JPEG2000. JPEG2000 is the new standard for image compression. We briefly described the core algorithms for JPEG2000 standard and its several features desirable in many interactive multimedia applications. The core compression algorithm has three major components - discrete wavelet transform (DWT), fractional bit plane coding (BPC), and context adaptive binary arithmetic coding. DWT and BPC are very computationally, as well as memory expensive operations. As a result, special purpose VLSI implementations of these algorithms are desirable for many devices to compress large size images in real time. Traditionally, the DWT is realized by convolution based finite impulse response (FIR) filtering techniques. However, Lifting based implementation of DWT is found to be computationally efficient and suitable for VLSI implementations. The basic principle behind the lifting based scheme is to decompose the finite impulse response filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementation have been recommended in JPEG2000 standard. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we reviewed some of the key lifting architectures suitable for VLSI implementation. The embedded block coding with optimized truncation (EBCOT) algorithm has been adopted for computation of BPC in JPEG2000. This algorithm is complex and inefficient to implement in a general purpose machine. We have described a special purpose architecture suitable for VLSI implementation of EBCOT algorithm. We also reviewed some elegant architectures in the literature which exploit the underlying data and computational parallelism inherent in the EBCOT algorithms. We also presented a top-level systems architecture for VLSI implementation of the JPEG2000 standard.

VLSI Algorithms and architectures for JPEG2000

In this paper, we presented VLSI algorithms and architectures for JPEG2000. JPEG2000 is the new standard for image compression. We briefly described the core algorithms for JPEG2000 standard and its several features desirable in many interactive multimedia applications. The core compression algorithm has three major components - discrete wavelet transform (DWT), fractional bit plane coding (BPC), and context adaptive binary arithmetic coding. DWT and BPC are very computationally, as well as memory expensive operations. As a result, special purpose VLSI implementations of these algorithms are desirable for many devices to compress large size images in real time. Traditionally, the DWT is realized by convolution based finite impulse response (FIR) filtering techniques. However, Lifting based implementation of DWT is found to be computationally efficient and suitable for VLSI implementations. The basic principle behind the lifting based scheme is to decompose the finite impulse response filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementation have been recommended in JPEG2000 standard. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we reviewed some of the key lifting architectures suitable for VLSI implementation. The embedded block coding with optimized truncation (EBCOT) algorithm has been adopted for computation of BPC in JPEG2000. This algorithm is complex and inefficient to implement in a general purpose machine. We have described a special purpose architecture suitable for VLSI implementation of EBCOT algorithm. We also reviewed some elegant architectures in the literature which exploit the underlying data and computational parallelism inherent in the EBCOT algorithms. We also presented a top-level systems architecture for VLSI implementation of the JPEG2000 standard.

Bit-split string-matching engines for intrusion detection and prevention

Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network and at the heart of almost every modern intrusion detection system is a string-matching algorithm. String matching is one of the most critical elements because it allows for the system to make decisions based not just on the headers, but the actual content flowing through the network. Unfortunately, checking every byte of every packet to see if it matches one of a set of thousands of strings becomes a computationally intensive task as network speeds grow into the tens, and eventually hundreds, of gigabits/second. To keep up with these speeds, a specialized device is required, one that can maintain tight bounds on worst-case performance, that can be updated with new rules without interrupting operation, and one that is efficient enough that it could be included on-chip with existing network chips or even into wireless devices. We have developed an approach that relies on a special purpose architecture that executes novel string matching algorithms specially optimized for implementation in our design. We show how the problem can be solved by converting the large database of strings into many tiny state machines, each of which searches for a portion of the rules and a portion of the bits of each rule. Through the careful codesign and optimization of our architecture with a new string-matching algorithm, we show that it is possible to build a system that is 10 times more efficient than the currently best known approaches.

A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm

Image feature separation is a crucial step for image segmentation in computer vision systems. One efficient and powerful approach is the unsupervised clustering of the resulting data set; however, it is a very computationally intensive task. This paper presents a high-performance architecture for unsupervised data clustering. This architecture is suitable for VLSI implementations. It exploits paradigms of massive connectivity like those inspired by neural networks, and parallelism and functionality integration that can be afforded by emerging nanometer semiconductor technologies. By utilizing a "global-quasi-systolic, local-hyper-connected" architectural approach, the hardware can process real-time DVD-quality video at the highest rate allowed by the MPEG-2 standard. The architecture is a realization of the histogram peak-climbing clustering algorithm, and it is the first special-purpose architecture that has been proposed for this important problem. The architecture has also been prototyped using a Xilinx field programmable gate array (FPGA) development environment. Although this paper discusses a computer vision application, the architecture presented can be utilized in the acceleration of the clustering process of any type of high-dimensionality data.

Efficient assignment and scheduling for heterogeneous DSP systems

This paper addresses high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpose architecture synthesis, an important problem is how to assign a proper FU type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve the heterogeneous assignment problem, i.e., how to assign proper FU types to applications such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained in the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove that the heterogeneous assignment problem is NP-complete. Efficient algorithms are proposed to find an optimal solution when the given DFG is a simple path or a tree. Three other algorithms are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost compared with the previous work.

A High Throughput String Matching Architecture for Intrusion Detection and Prevention

Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of almost every modern intrusion detection system is a string matching algorithm. String matching is one of the most critical elements because it allows for the system to make decisions based not just on the headers, but the actual content flowing through the network. Unfortunately, checking every byte of every packet to see if it matches one of a set of ten thousand strings becomes a computationally intensive task as network speeds grow into the tens, and eventually hundreds, of gigabits/second. To keep up with these speeds a specialized device is required, one that can maintain tight bounds on worst case performance, that can be updated with new rules without interrupting operation, and one that is efficient enough that it could be included on chip with existing network chips or even into wireless devices. We have developed an approach that relies on a special purpose architecture that executes novel string matching algorithms specially optimized for implementation in our design. We show how the problem can be solved by converting the large database of strings into many tiny state machines, each of which searches for a portion of the rules and a portion of the bits of each rule. Through the careful co-design and optimization of our our architecture with a new string matching algorithm we show that it is possible to build a system that is 10 times more efficient than the currently best known approaches.

Generating multimedia content with cellular automata

Researchers have long used cellular automata (CA), and in general parallel generative devices such as Lindenmayer systems, to produce images, fractals, growth, patterns in two dimensions, and sound. They usually implement these models on special-purpose architectures that often depend on the type of presentation being generated. This paper discusses the developed prototype for generating content, called extended cellular automata with pluggable multimedia elements (ExcapeMe). This prototype acts as an open environment that lets users execute CA in three dimensions and manage simultaneous rendering of CA using different forms of presentation. In principle, we can attach any type of multimedia presentation as a plug-in. The environment already supports ID, 2D, 2.5D, and 3D presentations, and we can apply sound rendering to CA of any dimension. The environment also supports interactively denning, editing, and executing CA as well as defining the mapping between the CA configurations and their actual rendering.

The Shared Control Parallel Architecture Model

SIMD machines are considered special purpose architectures chiefly because of their inability to support control parallelism. This restriction exists because there is a single control unit that is shared at the thread level; concurrent control threads must time-share the control unit (they are sequentially executed). We present an alternative model for building centralized control architectures that allows better support for control parallelism. This model, called shared control, shares the control unit(s) at the instruction level. More precisely, in each cycle the control signals for all the supported instructions are broadcast to the PEs. In turn, each PE receives its control by synchronizing with the control unit responsible for its local instruction. The shared control model is fundamentally different from the SIMD model. There are a number of architectural issues that must be resolved in order for this model to be useful. This paper identifies some of these issues and discusses their respective trade-off spaces. An integrated shared-control/SIMD architecture design (SharC) is presented and used to demonstrate the relative performance relative to a SIMD architecture.

A Configurable Logic Based Architecture for Real-Time ContinuousSpeech Recognition Using Hidden Markov Models

An architecture is presented for real-time continuous speech recognition based on a modified hidden Markov model. The algorithm is adapted to the needs of continuous speech recognition by efficient encoding of the state space, and logarithmic encoding of the weights so that products can be computed as sums. The paper presents the algorithm and its application related modifications, the mapping of the algorithm to a special purpose architecture, and the detailed design of this architecture using configurable logic. Emphasis is given on how the attributes of the algorithm are exploited in a configurable logic based design. A concrete design example is presented with a coprocessor engine having one large FPGA, 64 Mbytes of synchronous DRAM (SDRAM), a small FPGA as a SDRAM controller, and 2 Mbytes SRAM. This engine operating at 66 MHz performs roughly nine times as fast as a high end personal computer running a fully optimized version of the same algorithm.

Architectures for real-time volume rendering

Over the last decade, volume rendering has become an invaluable visualization technique for a wide variety of applications. This paper reviews three special-purpose architectures for interactive volume rendering: texture mapping, VIRIM, and VolumePro. Commercial implementations of these architectures are available or underway. The discussion of each architecture will focus on the algorithm, system architecture, memory system, and volume rendering performance.

Modelling And Simulation Of A Programmable Image Processor Using Hardware Simulation Systems

The real-time measurement and analysis of various road traffic parameters such as vehicle count, speed of vehicles, type of vehicles, and the turning movements of vehicles at traffic junctions (TMJ) etc. are increasingly required for traffic control and management. The image processing technique is now considered as an attractive and flexible technique for automatic analysis and data collection in traffic engineering. However, the computational requirement for such a technique is beyond the capacity of conventional computers, therefore, special purpose architectures have to be designed to speed up image processing operations. In this paper we describe a programmable image processor for measuring road traffic parameters such as vehicle count and TMJ parameters. The processor is designed with a high degree of parallelism to speed up image processing operations. Combining data parallelism found in array processors into the architecture of the processor, a high degree of concurrency is achieved. The processor is modelled and simulated using VHDL language. We execute image-processing algorithms on the simulation model and measure the performance of the whole system. The results show that the system is able to measure traffic parameters in real-time.