Specific Integrated Circuit Research Articles

Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

ClothFace: A Batteryless RFID-Based Textile Platform for Handwriting Recognition

This paper introduces a prototype of ClothFace technology, a battery-free textile-based handwriting recognition platform that includes an e-textile antenna and a 10 × 10 array of radio frequency identification (RFID) integrated circuits (ICs), each with a unique ID. Touching the textile platform surface creates an electrical connection from specific ICs to the antenna, which enables the connected ICs to be read with an external UHF (ultra-haigh frequency) RFID reader. In this paper, the platform is demonstrated to recognize handwritten numbers 0–9. The raw data collected by the platform are a sequence of IDs from the touched ICs. The system converts the data into bitmaps and their details are increased by interpolating between neighboring samples using the sequential information of IDs. These images of digits written on the platform can be classified, with enough accuracy for practical use, by deep learning. The recognition system was trained and tested with samples from six volunteers using the platform. The real-time number recognition ability of the ClothFace technology is demonstrated to work successfully with a very low error rate. The overall recognition accuracy of the platform is 94.6% and the accuracy for each digit is between 91.1% and 98.3%. As the solution is fully passive and gets all the needed energy from the external RFID reader, it enables a maintenance-free and cost-effective user interface that can be integrated into clothing and into textiles around us.

Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

A PUF-based mutual authentication scheme for Cloud-Edges IoT systems

Abstract With the exponential growth of generated and processed Internet of Things (IoT) data, the Cloud-Edges (CE) paradigm, which distributes part of the intelligence and computation burden among edge nodes while adopting cloud services only for heavyweight computation, has emerged as a valuable solution to lower latency and improve efficiency. Despite the clear benefits, the lack of centralized control and the exposure of user sensitive data make CE architectures particularly prone to data tampering and spoofing attacks, thus urging the implementation of effective security mechanisms, including in particular authentication. Unfortunately, due to the relatively small computing resources of involved nodes, implementing traditional cryptography-based security solutions is often not viable. To overcome this issue, in this paper we propose a mutual authentication scheme relying upon the adoption of Physically Unclonable Functions (PUFs), special integrated circuits provided with unclonability, uniqueness and tamper-evident properties. The proposed scheme was specifically designed to meet the computation and storage capabilities of the different devices that are typically involved in a CE system, and was proven to be effective against several known attacks while introducing a relatively low overhead.

An Integrated Circuit Solution to Johnson Noise Thermometry Using Low-Cost and Fast CMOS Technology

An integrated circuit solution to Johnson noise thermometry (ICJNT) using a low-cost and fast complementary metal–oxide–semiconductor (CMOS) technology is investigated in this paper. Benefits from both noise thermometry and integrated circuits (ICs) can be maintained in ICJNTs, which cost significantly less, work orders of magnitude faster than discrete-device JNTs, and can be applied to various applications. As a first attempt at an ICJNT, this paper presents the relevant analysis and design techniques, demonstrates the potential benefits of ICJNTs, and discusses the challenges unique to integrated circuit solutions. A prototype IC chip is fabricated using the 0.13- $\mu \text{m}$ CMOS technology with fully on-chip circuits, including sensing resistors, a pre-amplifier, and a flash analog-to-digital converter. To demonstrate the efficacy, a test PCB for the ICJNT was developed and measured in a standard industrial thermal chamber with a laboratory grade platinum resistance thermometer as a comparison reference. The test results show that this first ICJNT prototype is able to provide temperature measurement from 0 °C to 70 °C. The maximum deviation with two-point calibration is 1.2 °C at a measurement of 40 °C due to systematic error, and the standard deviation is approximately 2 °C. The measurement time is only 10 ms due to the fast IC technology. These results established the feasibility of the ICJNT concept. Since the ICJNT is a complete solution without discrete devices and the sensing resistors are not limited to specific IC materials, the ICJNT can be applied to various emerging applications, such as electric vehicles and microelectromechanical systems.

Upgrading a Detector for Studying Fast Processes on a Beam of Synchrotron Radiation

The current stage of the upgrade of the DIMEX detector for studying fast processes on a synchrotron radiation (SR) beam is described. The current version of the DIMEX is a one-dimensional high-pressure ionization chamber with a fast electron component readout. The detector can record photon fluxes from each bunch separately without mixing photons from different bunches. The maximum flux the DIMEX can detect is limited by the space charge of positive ions in a high-pressure gas. To substantially improve this and other parameters of the detector, it was decided to switch to microstrip silicon technology. A prototype based on a silicon-microstrip sensor was developed along with a special integrated circuit (ASIC) for reading out the signals from this prototype. The first tests of the new DIMEX-Si prototype on an SR beam show that it is superior to the gaseous version in all respects. Results are presented from the first tests of the silicon-microstrip detector prototype on the SR beam of the VEPP-4M storage ring.

Non-contact wafer thickness measurement of capacitance sensor circuit based on CAV424

Non-contact wafer thickness measurement with the CAV424 capacitance sensor special integrated circuit and arc pole plate capacitor sensor has good stability and linearity under low capacity of the bottom of sensor and lowe C condition. This method has a high technical advantages and practical value. Two capacitance sensors Cb, Ca measurement spacing 4mm install at the same axis which constitutes the size condition for measuring thickness. The static capacity of Ca and Cb is a constant value. The capacity of Cb and Ca will change when the silicon wafer is involved. This change is checked by the CAV424 capacitive sensor which has better linearity and higher thickness resolution.

Portable electrocardiograph through android application.

An electrocardiograph was designed and implemented, being capable of obtaining electrical signals from the heart, and sending this data via Bluetooth to a tablet, in which the signals are graphically shown. The user interface is developed as an Android application. Because of the technological progress and the increasing use of full portable systems, such as tablets and cell phones, it is important to understand the functioning and development of an application, which provides a basis for conducting studies using this technology as an interface. The project development includes concepts of electronics and its application to achieve a portable and functional final project, besides using a specific programmable integrated circuit for electrocardiogram, electroencephalogram and electromyogram, the ADS1294. Using a simulator of cardiac signals, 36 different waveforms were recorded, including normal sinus rhythm, arrhythmias and artifacts. Simulations include variations of heart rate from 30 to 190 beats per minute (BPM), with variations in peak amplitude of 1 mV to 2 mV. Tests were performed with a subject at rest and in motion, observing the signals obtained and the damage to their interpretation due to the introduction of muscle movement artifacts in motion situations.

特殊IC板引脚焊点缺陷检测中景深的研究

特殊IC板引脚焊点缺陷检测中景深的研究

Research on Brushless DC Motor Control System for Electric Vehicle

In order to improve the controllability and safety of electric vehicle, the flexibility of the motor control system, and ensure the service life of the motor controller, a kind of brushless DC motor control system that used microcontroller with special integrated circuits is suggested in this paper. Introduced the control scheme and operational principle of the control system, given the main hardware circuit, and expounded the control strategy and software design of system. In this control system, the microcontroller is mainly used to control special integrated circuits, implement good man-machine conversation and control strategy, as well as the management of the lead-acid battery; Special integrated circuits main to control the motor, alleviate the pressure of microcontroller effectively, guarantee the microcontroller to complete other work better. The test result indicates that the control system have a simple structure, response quickly, good reliability.

Development of a transparent photon detector for the online monitoring of IMRT beams

Introduction External beam radiotherapy performance has been increased by the emergence of state-of-the-art techniques, which improve local irradiation while preserving surrounding organs. They require consistent Quality Assurance (QA) programs, supported by Electronic Portal Imaging Devices and Dynalog files. Nevertheless, they do not enable accurate dose-monitoring during online delivery sessions. In the framework of the INSPIRA project, the DAMe group, in collaboration with the Radiotherapy Department of CHUG, is developing an innovative Transparent Detector for Radiotherapy (TraDeRa). The beam modulated by the Multileaf Collimator will be monitored ahead of the patient, in real-time, without dead zone. Material and methods Current version of this detector is a 1:4 scale prototype, partially instrumented. Basically, it consists in a matrix of ionization chambers. First, we measured the dose with a PTW 0.3 cc ionization chamber, in standard conditions, with and without embedding TraDeRa, to quantify detector-induced attenuation. Then, the detector was irradiated using a 14 square cm beam. Inhouse front-end electronics allows the amplitude of each pulse to be extracted, providing dose rate at the pulse scale. Finally, TraDeRa was irradiated with a 3 mm sliding slit. A real-time map of the signal every 50 ms is provided. Results The detector induces a 0.6% attenuation of the beam. Global accuracy and stability of TraDeRa was verified. We highlighted dose rate noticeable variations during the irradiation. Amplitudes of delivered pulses vary around 5% of the mean value, and up to 25% for the first pulse. Accurate monitoring of leaf position was obtained. The interleaf leakage appears clearly and represents a non-negligible contribution to the dose. Recently, a specific integrated circuit has been designed by the LPSC microelectronics group. It represents a key-step for the forthcoming embedded electronics. Conclusion The current version of TraDeRa already shows promising results for IMRT-QA. It is quite transparent so that it does not hinder the irradiation, while keeping the beam upstream of the patient under constant control. It will offer both suitable precision on 2D-beam characterization and real-time measurements at the pulse scale or every 50 ms. The development of the final prototype, with all embedded electronics, is in progress and is expected by the end of 2013.

A Soldering Defect Inspection System of a Special Integrated Circuit Board Based on Computer Vision

This paper introduces a soldering defect inspection system for a special integrated circuit board aided by the computer vision. Space occluder is fixed on this special integrated circuit board, which makes the light blocked from the CCD camera to the chip pins to be inspected. This system can inspect the light blocked soldering defects of the chip pins through the structure design of hardware system and the software system. It is a cheap but automatic soldering defect inspecting system, and can do the soldering defect detection instead of manual visual inspection, and improve the detection speed and stability.

A New Design Method of the Milling Machine Headstock Based on Frequency Converter Technology

After discuss how to select frequency range and design speed diagram, a new kind of milling machine headstock is proposed in this paper. The design of the frequency converter is discussed as well. The hardware of frequency converter contains main circuit and control circuit. Main circuit includes rectifier and inverter. Control circuit is made up of single-chip microcomputer and specific integrated circuit. In the new kind of milling machine, the spindle box is simplified at the same time.

Implementation of Transient Signal Detection Algorithms on FPGA

transient signals are non-periodic and discrete obtained from high energy physical processes in space. Most challenging issues in transient signal detection are the speed and accuracy with which a signal can be detected. Cumulative Sum (CUSUM) algorithm has been employed in this paper for transient signal detection and proved to be capable of meeting the necessary requirements. However, as ordinary software- based programs are unable to handle large scale sample of signals, the current research focuses on implementing the CUSUM algorithm on Field Programmable Gate Array (FPGA) which is a specific integrated circuit within the field of semi-customized circuits that can greatly enhance the speed of detection and analysis. Therefore a FPGA-based system was devoted to implement the algorithms for an efficient transient signal detection. A detection speed of 64 ns per sample set was achieved via implementation the algorithm on an Altera Cyclone IV device with a clock speed of 50 MHZ. The analyzed result shows the power consumption of the FPGA based system can be reduced to 136.75 mW. KeywordsSignal Processing, CUSUM Algorithm, FPGA Implementation

Wireless Measurement of RFID IC Impedance

Accurate knowledge of the input impedance of a radio-frequency identification (RFID) integrated circuit (IC) at its wake-up power is valuable as it enables the design of a performance-optimized tag for a specific IC. However, since the IC impedance is power dependent, few methods exist to measure it without advanced equipment. We propose and demonstrate a wireless method, based on electromagnetic simulation and threshold power measurement, applicable to fully assembled RFID tags, to determine the mounted IC's input impedance in the absorbing state, including any parasitics arising from the packaging and the antenna-IC connection. The proposed method can be extended to measure the IC's input impedance in the modulating state as well.

From human skin to Nano-Skin: an experimental study on human skin temperature measurement

The human state in human–machine systems should be monitored to improve system performance. In monitoring it is preferable to use physiological cues such as skin temperature. The sensing capabilities of human skin were analyzed. The sensing system of human skin was modeled, and inspired the design of a Nano-Skin for physiological measurement in dynamic human–machine contact for human state recognition. The Nano-Skin involves a flexible bottom layer, sensors, special integrated circuit, interconnection between sensors and special integrated circuit, and flexible top layer. The requirements for the sensors of a Nano-Skin are summarized, and compared with common sensors, MEMS sensors, and nano sensors. A Nano-Skin with deposited platinum was manufactured. The manufacturing process is shown to be feasible and repeatable. The Nano-Skin with deposited platinum was used to measure skin temperature. Its performance was investigated using experiments. The results verified that the accuracy of the Nano-Skin sensors will not be lower than Pt1000Ω. Smaller sensors in a Nano-Skin generally have better performance.

Development of Superconducting NbSi TES Array and Associated Readout With SQUIDs and Integrated Circuit Operating at 2 K

To further increase the sensitivity of future telescope projects dedicated to photometric astronomy observation at millimeter and sub-millimeter wavelengths, large number of bolometer is currently developed. In this context, The DCMB (Developement Concerte de Matrice de Bolometre) French collaboration makes an R&D effort to develop large bolometer arrays. This paper concentrates on a first demonstration of NbSi TES (transition-edge sensors) array development: a 23 NbSi (niobium silicon) superconducting thermometer array. Firstly, the NbSi thin film alloy is described then the 23 TES array topology is presented. The readout of large TES arrays requires ultra low noise amplification and multiplexing electronics. The use of a first stage transducer such as a SQUID (superconducting quantum interference device) allows ultimate performances in terms of noise. However, the linearization of the SQUID characteristic requires a low noise amplifier (LNA) to generate a flux lock loop (FLL). We implement this component in a cryogenic SiGe integrated circuit (IC) that could also contains the control of the multiplexing. Using this readout chain, a one-pixel operation using NbSi thermometer readout by SQUID and a cryogenic LNA is demonstrated. Finally, the development of a specific cryogenic IC including amplifiers, addressing and switching current sources needed for a 24 to 1 time domain SQUID multiplexer is presented.

Practical design of robots operating in radiation environments

Nuclear robots must be hardened against radiation for effective operation in high-radiation environments. These robots require special components that usually have few functions, high costs and long delivery times. In the present study, we propose a modulated and hierarchical electrical circuit system for robot components such as actuators. The hierarchical system is set into a design that can withstand radiation without reducing or limiting the functionality of the robot. The hierarchical system is achieved by minimizing the variety of integrated circuit (IC) components to be used and selecting specific ICs that require radiation testing. These ICs are defined by spotted ICs with regard to the integration density and operational speed. In some cases, it is possible to select off-the-shelf IC components, but certain key IC components are needed for on-line irradiation tests, depending on robot operation reliability and the radiation environment. Since the serial numbers of off-the-shelf IC components are random, it is important that a sufficiently large number of IC components are tested under the operating conditions for statistical evaluation. If the radiation lifetime is random, then the radiation lifetime of the sorted IC components can be estimated statistically. Here, the robot user decides the operation based on this lifetime. By doing so, the experimental cost can be minimized in accordance with the proposed method at the user's operational risk. Of course, if on-line irradiation tests are performed for various types of IC components, the radiation lifetime of the robot can be predicted with a relatively high accuracy. As a result, the design of a robot that operates under certain radiation conditions, while having a certain lifetime and cost, is possible. This design technique was applied to a nuclear disaster prevention robot and the radiation lifetime of the spotted IC components was shown to be distributed randomly, indicating the validity of the proposed method.

The design of VMEbus bridge controller with SHARC bus

Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.

The Magnitude of Potential Exposure-Tool-Induced Critical Dimension and Overlay Errors in Double Dipole Lithography for the 65-nm and 45-nm Technology Nodes

Double dipole lithography (DDL, DDL is a trademark of ASML Masktools.) is a viable imaging solution for the 65-nm and 45-nm technology nodes, when using ArF exposure tools. By taking advantage of the extreme off-axis illumination of the dipole, the demonstrated, small critical dimension (CD) can be resolved with a good process window. In this case k1 will be 0.31 when applying formula k1 = (minimum half pitch) × (wavelength, λ)/(numerical aperture, NA), the Rayleigh's resolution equation with minimum half pitch of 80 nm as well as wavelength and NA of 193 nm and 0.75, respectively. The detailed CD measurement data and process window analysis can be seen. The ability of the dipole to resolve this CD, however, applies only to structures that are perpendicular to the orientation of the dipole; i.e., the x-dipole (or horizontal dipole) resolves small, vertical lines and spaces [S. Hsu, N. Corcoran, M. Eurlings, W. Knose, T. Laidig, K. E. Wampler, S. Roy, X. Shi, M. Hsu, J. F. Chen, J. Finders, R. J. Socha and M. Dusa: SPIE 4691 (2002), 476]. The use of the pattern decomposition [S. Hsu, N. Corcoran, M. Eurlings, W. Knose, T. Laidig, K. E. Wampler, S. Roy, X. Shi, M. Hsu, J. F. Chen, J. Finders, R. J. Socha and M. Dusa: SPIE 4691 (2002) 476, S. Hsu, J. F. Chen, N. Cororan, W. Knose, D. J. Van Den Broeke, T. Laidig, K. E. Wampler, X. Shi, M. Hsu, M. Eurlings, J. Finders, T. B. Chiou, R. J. Socha, W. Conley, Y. W. Hsieh, S. Tuan and F. Hsieh: SPIE 5040 (2003) 215] and double exposure of the x-dipole and the y-dipole respectively, make it possible to image an arbitrary device pattern. DDL allows integrated circuit (IC) manufacturers to maintain their roadmaps for shrinking device technology, while extending the use of ArF technology. Compared with other low-k1 imaging solutions, DDL has the advantage of using standard mask technologies, such as binary masks or 6% attenuated phase shift masks (PSMs). Because of the lower cost and faster turn-around time of these masks, DDL has the potential to become the imaging solution of choice for small-volume IC products, such as many application specific IC devices (ASICs). The imaging performance of DDL and the pattern decomposition algorithm are discussed elsewhere [M. Eurlings, E. van Setten, J. A. Torres, M. Dusa, R. Socha, L. Capodieci and J. Finders: SPIE 4404 (2001) 266, S. Hsu, N. Corcoran, M. Eurlings, W. Knose, T. Laidig, K. E. Wampler, S. Roy, X. Shi, M. Hsu, J. F. Chen, J. Finders, R. J. Socha and M. Dusa: SPIE 4691 (2002) 476, S. Hsu, J. F. Chen, N. Cororan, W. Knose, D. J. Van Den Broeke, T. Laidig, K. E. Wampler, X. Shi, M. Hsu, M. Eurlings, J. Finders, T. B. Chiou, R. J. Socha, W. Conley, Y. W. Hsieh, S. Tuan and F. Hsieh: SPIE 5040 (2003) 215]. In this paper, we investigate the CD and overlay (OL) errors caused by exposure tools, such as the illuminator imperfections, for example; these errors include the error caused by the pole intensity imbalance (PIB), aberration induced CD errors, and image placement errors (IPEs). During our research, we carried out extensive simulations of 1-dimensional and 2-dimensional mask-pattern CD errors and IPEs as a function of the PIB, pole size, pole center location, and aberration sensitivity. Simulation results show that the magnitude of the IPE depends on the control of PIB, dipole telecentricity, and the pattern structures. We present an IPE and focus control budget to describe the necessary tool-control requirements, considering the device patterns that satisfy 65-nm and 45-nm technology nodes respectively. The available results show that we can control the sources of the exposure-tool errors, enabling DDL imaging technology to satisfy the requirements of the 65-nm and 45-nm technology nodes.