Spartan 3E Starter Kit Research Articles

Hardware Segmentation on Digital Microscope Images for Acute Lymphoblastic Leukemia Diagnosis Using Xilinx System Generator

Image segmentation is considered the most critical step in image processing and helps to analyze, infer and make decisions especially in the medical field. Analyzing digital microscope images for earlier acute lymphoblastic leukemia diagnosis and treatment require sophisticated software and hardware systems. These systems must provide both highly accurate and extremely fast processing of large amounts of image data. In this work, the hardware segmentation framework for Acute Lymphoblastic Leukemia (ALL) images based color histogram of Hue channel of HSV color space is proposed to segment each leukemia image into blasts and background using Field Programmable Gate Array (FPGA). The main purpose of this work is to implement image segmentation framework in a FPGA with minimum hardware resources and low execution time to be suitable enough for medical applications. Hardware framework of segmentation is designed using Xilinx System Generator (XSG) as DSP design tool that enables the use of Simulink models, implemented in VHDL and synthesized for Xilinx SPARTAN-3E Starter kit (XC3S500E-FG320) FPGA.

Performance of a new split digital phase lock loop in additive wideband Gaussian noise

SUMMARYThis paper proposes a new split digital phase lock loop (DPLL) in the presence of additive wideband Gaussian noise. The proposed new loop incorporates an additional phase modulation input along with its frequency modulation input in the digitally controlled oscillator of the loop. The present loop eliminates the deleterious effects of wideband Gaussian noise. A better output signal‐to‐noise ratio is achieved using the new split‐loop DPLL. In the design of the loop, the interaction between the loop and the radio frequency filters is avoided by using an in‐phase and quadrature‐phase digitally control oscillator. The proposed split‐loop DPLL is simulated using MATLAB (The MathWorks, Natick, MA, USA)/Simulink environment and System Generator, a tool from Xilinx (Xilinx, Inc., San Jose, CA, USA) used for field programmable gate array design, as well as implemented on a Spartan 3E Starter Kit board. The design is implemented on field programmable gate array using the VHDL [Very High Speed Integrated Circuit (VHSIC) Hardware Description Language] language on Xilinx ISE 13.1. The proposed split‐loop DPLL proves to be better than the conventional split‐loop DPLL from the standpoint of the settling time, the peak time, the rise time, and the peak overshoot as well as from the standpoint of the BER performance for a typical binary phase‐shift keying system and validates against the MATLAB/Simulink results. Copyright © 2013 John Wiley & Sons, Ltd.

An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320) exceeds those of similar or greater resources architectures. The proposed architecture reduces the resources available on target device by 50%.

A Spartan3E-based low-cost system for gamma-ray detection in small single photon emission computed tomography or positron emission tomography systems

The development and assessment of a readout system based on field programmable gate arrays (FPGA) for dedicated nuclear medicine cameras is presented. We have used Xilinx Spartan3E starter kit, which is one of the simplest FPGA evaluation boards. The aim of this work is to offer a simple, open source, data acquisition tool, which provides accurate results for nuclear imaging applications. The system has been evaluated using three different experimental setups: pulses from two position-sensitive photo-multipliers (PSPMTs) and a silicon photo-multiplier (SiPM) were recorded, using 99mTc sources. Two dual channel, external, 12 bit analog to digital converters with a sampling rate of 1 Msps per channel were used. The tool was designed using Xilinx's embedded development kit and was based in Xilinx's Microblaze soft-core processor. A reference multiparameter-based data acquisition system using nuclear instrumentation modules was used for the evaluation of the proposed system. A number of tests were carried out to assess different algorithms for pulse maximum estimation and Gaussian fitting provided optimal results. The results have shown that the FPGA data acquisition system (i) provides accurate digitization of the PSPMT anode signals under various conditions and (ii) gives similar energy spectra when SiPMs are used.