Spartan-6 Field Programmable Gate Array Research Articles

Design and implementation of deep neural network hardware chip and its performance analysis

The artificial neural network (ANN) with a single layer has a limited capacity to process data. Multiple neurons are connected in the human brain, and the actual capacity of the brain lies in the interconnectedness of multiple neurons. As a specified generalization of ANN deep learning makes use of two or more hidden layers, which implies that a greater number of neurons are required to construct the model. A network that has more than one hidden layer, also known as two or more hidden layers, is referred to as a deep neural network, and the process of training such networks is referred to as deep learning. The research article focuses on the design of a multilayer or deep neural network presented for the target field programmable gate array (FPGA) device spartan-6 (xc6stx4-2t9g144) FPGA. The simulation is carried out using Xilinx ISE and ModelSim software. There are two hidden layers in which (2×1) multiplexer blocks are utilized for processing twenty neurons into the output of ten neurons in the first hidden layer and demultiplexers (1×2) and vice versa. The hardware utilization is estimated on FPGA to compute the performance of the deep neural hardware chip based on memory, flip flops, delay, and frequency parameters. The design is scalable and applicable to various FPGA devices, which makes the work novel. FPGA-based neuromorphic hardware acceleration platform with high speed and low power for discrete spike processing on hardware with great real-time performance.

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

The application of Verilog in the development of casual games

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.

MS-LW-TI: Primitive-Based First-Order Threshold Implementation for 4 × 4 S-boxes

Threshold implementation (TI) is a lightweight countermeasure against side-channel attacks when glitches happen. As to masking schemes, an S-box is the key part to protection. In this paper, we propose a general first-order lightweight TI scheme for 4 × 4 S-boxes and name it as MiniSat-lightweight-threshold implementation (MS-LW-TI). First, we use MiniSat to optimally decompose an S-box into the least number of three different logic gate operations, AND, OR, and XOR. Among these operations, we define two primitives and the extension of two primitives for TI design. Furthermore, we prove that the primitives and their extensions strictly comply with the security properties. Finally, we implement MS-LW-TI on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) to show that the S-boxes of PRESENT, GIFT, and PICCOLO consume only 17, 15, and 13 look-up-tables (LUTs), 16, 9, and 16 flip-flops (FFs), 6, 5, and 6 slices, respectively. Compared with the existing lightweight TI design, our TI for PRESENT S-box has a 22%, 38%, and 25% reduction of LUTs, FFs, and slices to the design by Shahmirzadi and Moradi at IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2021, and our TI for GIFT S-box has a 6%, 25%, and 28% reduction of LUTs, FFs, and slices to the design by Jati et al., which is the smallest.

Vacuum Packaging Sensor Based on Time-Resolved Phosphorescence Spectroscopy

Intelligent food packaging with the multisensory analysis is promising as the next generation technology of food packaging. The oxygen content in food packaging is one of the crucial parameters affecting the food quality and shelf life. Caviar is among the most nutritious and costly food sources. Here, a photonic oxygen-sensing system, based on the time-resolved phosphorescence spectroscopy of a platinum complex, is developed for non-contact, non-intrusive, and real-time vacuum packaging quality control, and implemented for caviar packaging. The sensor is embedded in protective polyethylene layers and excited with a short-pulsed light emitting diode (LED) source. Integration of a blue pulsed light source, a fast and amplified silicon photodiode controlled by the Spartan-6 field programmable gate array (FPGA), and a long lifetime platinum complex results in a photonics-based oxygen sensor with a fast response and high sensitivity to the vacuum packaging damage, which is suitable for caviar. It is revealed that applying the polyethylene layers protects the caviar from the platinum complex, leaching while not interfering with the sensor functionality. Characterizing the photonic system based on its sensitivity, repeatability, stability, and long-term operation demonstrates its capability for this application.

Field programmable gate array based moving object tracking system for robot navigation

This paper proposes a method in which an object tracking robot system is implemented on field programmable gate arrays (FPGAs). The OV7670 camera provides real-time object pictures to the system. To improve picture quality, images are put via the median filter phase. The item is distinguished from the backdrop based on color (red), after which it is subjected to a mathematical morphological approach of filtering to eliminate noise. To send the robot control signals, the object's (new) coordinates are found. In this method, the median filter, color separation, hardware IP cores, and morphological filter are all part of the embedded system on FPGA. Through the direct memory access (DMA) controller, these cores may communicate and perform high-speed pipeline computing at higher data rates. The entire system is executed in real-time on Xilinx's spartan-6 FPGA KIT. The results show practical and promise.

Field Programmable Gate Array-Based Execution on a Distributed Energy Resource Supported Electrical Distribution System for Enhanced Power Quality with Optimal Active Power Flow Control

This paper explains the experimental study of a distributed energy resource (DER) integrated three-phase, three-wire electrical distribution system (EDS) under power quality (PQ) and optimal active power flow control (OAPFC). In this research, a back-to-back connected two-level VSI (BTB-TVSI) based distribution static compensator (DSTATCOM) for unbalanced non-linear load is designed. The aim is to provide better OAPFC in EDS with shunt compensation to maintain a round-the-clock quality power supply for end users. The improved neural network-based adaptive least mean square (ALMS) control algorithms are employed for DSTATCOM. The ALMS control strategy is realized using the SPARTAN-6 field programmable gate array (FPGA) evaluation kit. This research involves the comparative study of a two-level voltage source inverter (VSI) and a BTB-TVSI in terms of their OAPFC capability and robustness in mitigating power quality (PQ) against source current disturbances, low power factor (PF), poor voltage regulation, unbalanced voltage at the point of common coupling (PCC), high switching stress, and issues in the EDS operation. The experimental results demonstrate that the BTB-TVSI using an ALMS controller is able to achieve better dynamic performance and lower total harmonic distortion (THD) under selected/permissible limits in comparison to a conventional VSI.

High precision and real-time acquisition system for interface stress measurement in bridge bearing

Since the damage of the bridge structure may cause great disasters, it is necessary to monitor its health status, especially the bridge bearing, the important connecting component of the bridge's upper and lower structures. Nowadays, manual inspection is the main method to get the information of the bridge bearings’ work status. However, occasional damage of bridge bearing may not be detected in time, and sometime the installation position of the bearing makes the manual inspection on bridge bearing difficult and even impossible. Therefore, in order to know the work status of the bridge bearings timely, an intelligent remote monitoring system for the bridge bearing is developed. A 32-channel real-time acquisition system is designed by using an AD7768-1 analog-to-digital converter and Xilinx Spartan-6 Field Programmable Gate Array for interface stress continuously acquired in the bridge bearing. To assure the good linearity and low noise performance of the monitoring system, the data acquisition card is meticulously designed to reduce noise from both hardware and software and realize high-precision acquisition. Through the establishment of the monitoring server, the compressive stress data can be displayed synchronously and the overpressure situation can be alarmed in real-time. The experimental results show that the accuracy of the calibrated sensor is within 1.6%, and the detection error of the acquisition board is less than 200 μV. The acquisition system is deemed to have considerable advantages in accuracy and applicability.

FPGA‐based control strategy of five‐phase induction motor drives

Here, a novel control technique for Five-Phase Induction Motor (FPIM) drives using a field-programmable gate array (FPGA) controller is proposed. Open-loop control is analysed in terms of the performance and measurement of various power quality factors, such as voltage harmonics, current harmonics, total harmonic distortion, crest factor, unbalanced, short and long-term flickering, K-factor, real power, reactive power, apparent power, and power factor. This study experimentally demonstrated a closed-loop system with both PID and DTC controls for the FPIM. Diminished torque pulsation is obtained by efficiently utilizing the voltage vectors from the total states of 25 = 32. A novel EG voltage vector sequence was proposed for DTC techniques and compared with small, medium, and large voltage vector sequences. Proposed innovative control programming techniques in spartan-6 XC6SLX25 series FPGA for switching the five-phase two-level inverter to reduce the total harmonics distortion by less than 2%.

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.

Design and Implementation of UART Using FPGA Board

Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receiver, Transmitter, Microprogrammed Controller and Field Programmable Gate Array (FPGA).

A reconfigurable PUF structure with dual working modes based on entropy separation model

Privacy Protection Mutual Authentication (PPMA) in the Internet of Things uses physical unclonable functions (PUFs) and true random number generators (TRNGs) as security primitives, providing a lightweight solution for key generation and protection. At present, the designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) lack theoretical support, and have poor randomness and stability. Therefore, this paper provides a separation model of PUF entropy (manufacturing delay) and TRNG entropy (jitter delay) based on ring oscillators (ROs). Based on this model, a reconfigurable PUF structure is proposed, which can be reconstructed to a TRNG by changing the working mode. The proposed structure not only improves the area utilization, but also realizes the low-power consumption. Experiments on Xilinx Spartan-6 FPGAs and Xilinx Virtex-6 FPGAs show that the proposed structure has wonderful performance. The PUF has excellent uniqueness (average resolution is 50.21%) and reliability (the average repeatability rate is 96.98%). TRNG's output sequences have high randomness and pass all National Institute of Standards and Technology (NIST) tests (average pass rate is 99%).

Cost and energy efficient implementation of FPGA based home automation using Android platform

This paper presents the implementation of Spartan-3 Field programmable gate arrays (FPGA) based home automation by using the android platform. It involves each step used in the automation of the smart home through wireless communication and the operation of central devices. Most conspicuously, the android platform, Bluetooth and embedded systems have gained popularity in the electronics field. This paper will also go through a suitable method where users have control by using android applications over the operation of their domestic appliances by FPGA. The android application shall be beneficiary to the disabled and old age in a secure and efficient manner. This paper will also go through the unique cost-effectiveness of the current technologies and energy-saving solutions to the modern demands of smart homes.

Implementation and integration of image processing blocks in a real-time bottle classification system

A practical solution to the problems caused by the water, air, and soil pollution produced by the large volumes of waste is recycling. Plastic and glass bottle recycling is a practical solution but sometimes unfeasible in underdeveloped countries. In this paper, we propose a high-performance real-time hardware architecture for bottle classification, that process input image bottles to generate a bottle color as output. The proposed architecture was implemented on a Spartan-6 Field Programmable Gate Array, using a Hardware Description Language. The proposed system was tested for several input resolutions up to 1080 p, but it is flexible enough to support input video resolutions up to 8 K. There is no evidence of a high-performance bottle classification system in the state-of-the-art. The main contribution of this paper is the implementation and integration of a set of dedicated image processing blocks in a high-performance real-time bottle classification system. These hardware modules were integrated into a compact and tunable architecture, and was tested in a simulated environment. Concerning the image processing algorithm implemented in the FPGA, the maximum processing rate is 60 frames per second. In practice, the maximum number of bottles that can be processed would be limited by the mechanical aspects of the bottle transportation system.

RPPUF: An Ultra-Lightweight Reconfigurable Pico-Physically Unclonable Function for Resource-Constrained IoT Devices

With the advancement of the Internet of Things (IoTs) technology, security issues have received an increasing amount of attention. Since IoT devices are typically resource-limited, conventional security solutions, such as classical cryptography, are no longer applicable. A physically unclonable function (PUF) is a hardware-based, low-cost alternative solution to provide security for IoT devices. It utilizes the inherent nature of hardware to generate a random and unpredictable fingerprint to uniquely identify an IoT device. However, despite existing PUFs having exhibited a good performance, they are not suitable for effective application on resource-constrained IoT devices due to the limited number of challenge-response pairs (CRPs) generated per unit area and the large hardware resources overhead. To solve these problems, this article presents an ultra-lightweight reconfigurable PUF solution, which is named RPPUF. Our method is built on pico-PUF (PPUF). By incorporating configurable logics, one single RPPUF can be instantiated into multiple samples through configurable information K. We implement and verify our design on the Xilinx Spartan-6 field programmable gate array (FPGA) microboards. The experimental results demonstrate that, compared to previous work, our method increases the uniqueness, reliability and uniformity by up to 4.13%, 16.98% and 10.5%, respectively, while dramatically reducing the hardware resource overhead by 98.16% when a 128-bit PUF response is generated. Moreover, the bit per cost (BPC) metric of our proposed RPPUF increased by up to 28.5 and 53.37 times than that of PPUF and the improved butterfly PUF, respectively. This confirms that the proposed RPPUF is ultra-lightweight with a good performance, making it more appropriate and efficient to apply in FPGA-based IoT devices with constrained resources.

Design and Development of ROSMC-Based Single-Stage Z Source Inverter for Power Quality Enhancement in Hybrid Electric Vehicle Applications

This research work focuses on the design and analysis of the single-stage reduced order sliding mode control (ROSMC)-based Z-source inverter (ZSI) using sinusoidal pulse width modulation (SPWM) technique for improving the output power quality. To enhance the ZSI output voltage, the shoot-through (ST) mode is executed. Reduced 2nd order model of ZSI is derived from original 6th order model using moment matching method to reduce the sensor requirements and complexity in controller design. The closed loop control is accomplished using cascade control technique to investigate the system’s dynamic response. A Genetic Algorithm (GA)-tuned Proportional Integral (PI) controller is used for the outer voltage control. GA-tuned PI/ROSMC-based SPWM control technique has been attempted for inner current control. Sinusoidal reference signal is generated by the inner current control loop. Internal Model Control (IMC)-tuned Proportional Integral derivative (PID) controller is used to minimise the effect of Right Half-Plane zero, and it also produces required shoot-through duty ratio (STDR). Simulation results illustrate that the ROSMC-based SPWM technique provides superior performance than GA-tuned PI-based SPWM control technique. An experimental prototype model of 2 kW ZSI, ROSMC-based SPWM control is implemented using SPARTAN-6 field programmable gate array. The simulation results are substantiated with the hardware results.

FPGA Realization of ANFIS Controller Using a Proposed Digital Design

The design and realization of Adaptive Neuro-Fuzzy Inference System (ANFIS) controller based on Field Programmable Gate Array (FPGA) is presented in this paper. The controller intended to control the temperature of medical oven. A novel design of digital ANFIS is presented here for the implementation process. Different controllers are designed and their results are compared using MATLAB program to show the ANFIS superiority. The designed controllers tested for cell cultures application at 37.5. A reduction is made for the designed digital ANFIS due to the used FPGA limitations. The reduced design minimizes the utilized slices from 366% to 3% and LUTs from 364% to 3%. The reduced design reached an optimum size for this controller to utilize a smallest memory size. A real-time FPGA implementation of the proposed digital ANFIS have been done and verified through Xilinx ISE 14.6 using the VHDL language. The VHDL code for the controller is produced, aggregated and downloaded on the FPGA Spartan 3A/AN FPGA kit. A comparison between the simulation and implementation results is made. The matching between these results proves the effectiveness and robustness of the proposed digital ANFIS and the excellent performance of the FPGA based controller.

Design of High Speed and Low Area Confined Multiplier on FPGA

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

Design a novel digital sliding mode predictive control for buck converter

ABSTRACT In this article, a new discrete-time sliding mode predictive control (DSMPC) with a PID sliding function is proposed for synchronous DC–DC buck converter, and its stability analysis is reported. The model predictive control, along with digital sliding mode control (DSMC), is able to further reducing the chattering phenomenon, steady-state error, overshoot and undershoot. The proposed control implementation only requires output error voltage evaluation. The effectiveness of the proposed DSMPC is proved through simulation results executed by the MATLAB/SIMULINK software. These results demonstrate its superior performance to DSMC. In other words, it represents a significant reduction of the chattering, overshoot and undershoots of output voltage response by an optimised control law during load and line variations. The proposed DSMPC almost overcomes the steady-state error (0.02%) and decreases the ripple value to about 0.2%. The overshoot and undershoot are 1.5% and 1%, respectively. Moreover, when the input voltage is changed by 26%, there is approximately no overshoot and undershoot. Also, some experimental results are presented to further illustrate the effectiveness of the proposed system. Experimental studies have been performed using a Spartan-6 field programmable gate array platform by Xilinx for the implementation of the digital control and relevant logic.

Digital-to-time converter for test equipment implemented using FPGA DSP blocks

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.