Source-drain Series Resistance Research Articles

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.

Detailed electrical characterization of 200 mm CMOS compatible GaN/Si HEMTs down to deep cryogenic temperatures

A detailed electrical characterization and transistor parameter extraction on 200 mm CMOS compatible GaN/Si HEMTs was performed down to deep cryogenic temperatures. The main transistor parameters (threshold voltage Vth, low-field mobility μ0, subthreshold swing SS, source-drain series resistance Rsd) were extracted in linear region using the Y-function and the Lambert-W function methods for gate lengths down to 0.1 µm. The Y-function method was also employed in saturation region for the extraction of the saturation velocity. The results indicate that these GaN/Si HEMT devices demonstrate a very good functionality down to very low temperature with improvement of mobility and subthreshold slope. It was also shown by TLM analysis that the source-drain series resistance Rsd is more limited by the contact resistance than by the 2DEG access region resistance as temperature is lowered.

Giant Photoresponsivity and External Quantum Efficiency in a Contact‐Engineered Broadband a‐IGZO Phototransistor

AbstractBroadband photodetectors with a wide ultraviolet (UV)–visible (vis)–near‐infrared (NIR) spectral response reduce cost and form factors in smart sensing systems by using one rather than multiple devices for versatile applications. However, simultaneously achieving broadband detection, high responsivity, and fast response time remains challenging. This study demonstrates a high‐performance broadband amorphous In–Ga–Zn–O (a‐IGZO) phototransistor using an engineered Ni/Ti bilayer metal contact. This device differs drastically from the conventional a‐IGZO phototransistors in several aspects: 1) Pronounced photoresponse occurs at the device ON‐state rather than the OFF‐state. 2) A broadband response of 385–980 nm rather than a narrowband UV response. 3) Fast sub‐ms response time with no persistent photocurrent. 4) High responsivity of exceeding 105 A W−1. The external quantum efficiency exceeding 107% and specific detectivity exceeding 1015 Jones are also among the best of any UV–vis–NIR broadband photodetectors. The photoresponse is attributed to the light‐sensitive source–drain series resistance at the ON‐state. The Ni diffusion during postmetal annealing induces photoactive subgap states and modulates the conductivity of a‐IGZO at the contact region. The superior performance using low‐temperature processes and simple device structures as the widely available a‐IGZO technology suggests a tremendous application potential of this broadband phototransistor.

An Analytical Method for Parameter Extraction in Oxide Semiconductor Field-Effect Transistors

This article presents an analytical method for parameter extraction in oxide semiconductor field-effect transistors (OS FETs), including threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), effective channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ), source-drain series resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ), and intrinsic effective mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">int</sub> ). An analytical expression of effective mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) is implemented with the consideration of percolation conduction and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> effects. This method relies on the concept of Y-function method and the channel length dependent measurement. The extraction results are compared to those from the combination of transfer length method (TLM). It has been shown that a better accuracy of the extracted parameters is achieved with the proposed method. Furthermore, transfer characteristics are resimulated based on the extracted parameters, in which a good match between measurement and simulation is obtained.

Drain current local variability analysis in nanoscale junctionless FinFETs utilizing a compact model

This paper investigates the local variability in nanoscale triple-gate junctionless FinFETs utilizing an analytical symmetric and continuous compact model combined with Monte Carlo simulations. Initially, the device parameters are extracted from the experimental transfer characteristics, such as threshold voltage, ideality factor, low-field mobility, source-drain series resistance, channel length modulation factor and mobility degradation factor. Then, statistical analysis is performed to calculate the mean values and standard deviations of the differences of the aforementioned parameters for the local pairs and large number of devices with reference to the mean value of all dies. Monte Carlo simulations allow the compact model to reproduce successfully the drain current local variability. Most important process parameters have been considered and assessed as variability sources, by using the error propagation formula and exploiting the proposed drain current compact model. Successful application to experimental data, revealed the extent of the variabilities in most important process parameters of the devices (sources of variability).

Novel on-resistance based methodology for MOSFET electrical characterization

A new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd) = Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction free from source and drain series resistance.

Tuning Channel Architecture of Interdigitated Organic Electrochemical Transistors for Recording the Action Potentials of Electrogenic Cells

AbstractOrganic electrochemical transistors (OECTs) have emerged as versatile electrophysiological sensors due to their high transconductance, biocompatibility, and transparent channel material. High maximum transconductances are demonstrated facilitating the extracellular recording of signals from electrogenic cells. However, this requires large channel dimensions and thick polymer films. These large channel dimensions lead to low transistor densities. Here, interdigitated OECTs (iOECTs) are introduced, which feature high transconductances at small device areas. A superior device performance is achieved by systematically optimizing the electrode layout regarding channel length, number of electrode fingers and electrode width. Interestingly, the maximum transconductance (gmax) does not straightforwardly scale with the channel width‐to‐length ratio, which is different from planar OECTs. This deviation is caused by the dominating influence of the source–drain series resistance Rsd for short channel devices. Of note, there is a critical channel length (15 µm) above which the channel resistance Rch becomes dominant and the device characteristics converge toward those of planar OECTs. Design rules for engineering the performance of iOECTs are proposed and tested by recording action potentials of cardiomyocyte‐like HL‐1 cells with high signal‐to‐noise ratios. These results demonstrate that interdigitated OECTs meet two requirements of bioelectronic applications, namely, high device performance and small channel dimensions.

Study on the Lateral Carrier Diffusion and Source-Drain Series Resistance in Self-Aligned Top-Gate Coplanar InGaZnO Thin-Film Transistors

We investigated the lateral distribution of the equilibrium carrier concentration (n0) along the channel and the effects of channel length (L) on the source-drain series resistance (Rext) in the top-gate self-aligned (TG-SA) coplanar structure amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The lateral distribution of n0 across the channel was extracted using the paired gate-to-source voltage (VGS)-based transmission line method and the temperature-dependent transfer characteristics obtained from the TFTs with different Ls. n0 abruptly decreased with an increase in the distance from the channel edge near the source/drain junctions; however, much smaller gradient of n0 was observed in the region near the middle of the channel. The effect of L on the Rext in the TG-SA coplanar a-IGZO TFT was investigated by applying the drain current-conductance method to the TFTs with various Ls. The increase of Rext was clearly observed with an increase in L especially at low VGSs, which was possibly attributed to the enhanced carrier diffusion near the source/drain junctions due to the larger gradient of the carrier concentration in the longer channel devices. Because the lateral carrier diffusion and the relatively high Rext are the critical issues in the TG-SA coplanar structure-based oxide TFTs, the results in this work are expected to be useful in further improving the electrical performance and uniformity of the TG-SA coplanar structure oxide TFTs.

Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

In this letter, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

A comparative mismatch study of the 20 nm Gate-Last and 28 nm Gate-First bulk CMOS technologies

In this work the threshold voltage (Vt), the current gain factor (β), and the drain current (ID) mismatch trends for 20nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the β mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and β, and on the contributions of the transconductance divided by the drain current (Gm/ID) and the source drain series resistance (Rsd) terms. The 20nm Gate-Last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28nm Gate-First counterpart. The evolution of the Vt and β mismatch parameters, iAΔVt and iAΔβ/β, is further analyzed as a function of the electrical oxide thickness EOT (Tox) along the technology nodes from 90nm to 20nm. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot of iAΔVt as a function of EOT is observed starting at the 28nm Gate-First technology, with the offset approaching zero for the 20nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances.

Impact of various silicide techniques on SiGe source–drain series resistance and mobility of pMOSFETs

A comparative experimental study of series resistance and hole mobility of pMOSFETs with silicon germanium (SiGe) junctions under various silicide techniques is carried out. It is found that using an additional germanium pre-amorphous implant process in the nickel silicide (NiSi) techniques does not affect the hole mobility. However, it increases the source/drain series resistance. On the other hand, an additional silicon capping layer process in the NiSi techniques not only improves the hole mobility, but also reduces the series resistance dramatically. Various MOSFET characterizations from the silicide techniques are mainly due to the differences in the NiSi/SiGe interface structures in those devices.

“Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction

In this work, we extend the “Y function” method to the saturation regime of MOSFET operation. This allowed us for the first time to extract a low charge apparent mobility up to high drain voltage and consequently the saturation velocity without the need of source drain series resistance correction. The method has successfully been applied to silicon (Si) and germanium (Ge) bulk technologies and the nonconvergence of linear mobility and saturation velocity improvement is highlighted.

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

Higher-Order Effect of Source–Drain Series Resistance on Saturation Drain Current in Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

The saturation drain current including a higher-order effect of series resistance is investigated in sub-20 nm metal–oxide–semiconductor field-effect transistors (MOSFETs). The reduction in current by the resistance is calculated using a derived analytical current model. As a result, the reduction rate increases from 15.8 to 24.0% as the gate length decreases from 32 to 18 nm. Ratios of the Nth-order term to the sum of all absolute order terms are calculated. As the gate length decreases, the effect of higher-order terms becomes important for analyzing the effect of the series resistance. Normalized expansion components of the higher-order resistance-effect are compared with the reduction rate to determine the physical reasons for the reduction increase. We find that the ratio of the source resistance to the channel resistance is the dominant factor in device design and development for sub-20 nm MOSFETs.

Impact of Substrate Rotation and Temperature on the Mobility and Series Resistance of Triple-Gate SOI nMOSFETs

In this work a comparative experimental analysis of the electron mobility and parasitic source-drain series resistance of triple-gate n-channel MOSFETs as a function of the temperature is carried out. Devices with different fin widths fabricated on standard non-rotated and 45o rotated SOI substrates were analyzed for temperatures ranging from 250 K to 400 K. It is shown that the use of rotated substrate does not affect the subthreshold slope or the threshold voltage variation with temperature of these devices. On the other hand, the change in the conduction plane not only improves the mobility, but also promotes a rise of its variation with temperature. Although the fin width reduction may cause an increase of the series resistance, the increased mobility of rotated devices is responsible for the series resistance roll-off and this reduction becomes larger as the fin is narrowed.

Formation and Property of Yttrium and Yttrium Silicide Films as Low Schottcky Barrier material for n-Type Silicon

As the candidate for the low Schottky barrier material for n-type silicon, physical and electrical properties of yttrium and its silicide were investigated. In order to prevent both Si surface and easily-oxidized low work function metals from being oxidized, N2 sealed cleaning and transfer system and capping layer on low work function metals were employed. Fabricated Al/Y/p-type silicon Schottky barrier diode showed an excellent n-value. The extracted Schottky barrier height for electrons of yttrium silicide is as low as 0.3 eV. This result can be applied to form low contact resistivity silicide/n-type silicon contact, and contribute to lower the parasitic source drain series resistance of metal–oxide–semiconductor devices.

Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors

Ultra-thin Silicon-on-Insulator (SOI) transistor has proved to offer advantages over bulk MOSFETs for high-speed, low power applications. However, there is still a strong need to obtain an accurate understanding of carrier transport and mobility behaviour in these advanced devices. In this work, magnetoresistance technique is used to perform mobility measurements in Fully-Depleted Silicon-on-Insulator (FDSOI) MOSFETs. This technique has the advantage of allowing channel mobility measurement from weak to strong inversion without requiring the knowledge of the transistor’s effective channel length. The influence of different scattering mechanisms in the channel is investigated in details by obtaining mobility values at low temperatures. A new differential method enabling mobility extraction from pure channel magnetoresistance corrected for source–drain series resistance is presented. After the correction, in devices with large series resistance an increase in the extracted mobility is obtained in strong inversion, where the channel resistance is small and conventional mobility extraction is most affected by the impact of series resistance.

Influence of mobility model on extraction of stress dependent source–drain series resistance

The extraction of the parasitic source–drain series resistance after stress is a significant challenge, which has not been reported for channel lengths below 0.5 μm. Methods proposed until now yield a reducing series resistance behaviour for such channel lengths, contrary to expectation. We demonstrate that the underlying cause of this phenomenon is due to modification of mobility behaviour under stress. A new methodology for monitoring the time dependent progression of series resistance and mobility degradation for stress conditions varying from hot carriers to Negative Bias Temperature is proposed. A new threshold voltage model separating the effects of damaged and undamaged portions of a stressed device is also demonstrated.

Effects of uniaxial mechanical stress on drive current of 0.13 μm MOSFETs

We study the effects of both external mechanical stress and intrinsic stress due to trench isolation on drive currents of 0.13 /spl mu/m-node MOSFETs. The drive current, I/sub dsat/, of PMOS is enhanced by about 13% while that of NMOS is reduced by about 9% upon applying a uniaxial compressive stress along the channel of L/sub physical/=85 nm. The shifts in linear drive current, I/sub dlin/, are larger. By applying the external stress, we have simultaneously reproduced, for both PMOS and NMOS, the I/sub dsat/ and I/sub dlin/ shifts due to different gate-trench-isolation distances. We find that the shifts by the applied stress, /spl Delta/I/sub dsat//I/sub dsat0/ and /spl Delta/I/sub dlin//I/sub dlin0/, decrease with decreasing gate length. The change in total resistance, /spl Delta/(V/sub ds//I/sub dlin/), is a linear function of gate length. Because of the mobility dependence on external stress, we have also been able to extract source-drain series resistance, R/sub sd/, by simply bending the wafer.

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.