Source-coupled FET Logic Research Articles

Variable-ratio digital frequency dividers: Analogue design methodology and phase noise analysis based on harmonic balance

A unifying analogue description of the operation principle of digital dividers is proposed. A simple switched-ring oscillator is used as the basic block to build a reference model of fixed-ratio dividers, which is extended to variable-ratio dividers, serving as a design guide. The concept of variable-ratio digital frequency dividers as switched-ring oscillators justifies the proposal of a procedure for analyzing added phase noise across their whole operating bandwidth, based on a prior harmonic balance (HB) simulation and taking into account single transistor noise source models. Application of HB and Envelope-Transient simulation techniques to digital dividers is discussed. A 3–4 dual-modulus prescaler implemented in Source-Coupled FET Logic (SCFL) and manufactured in commercially available GaAs technology provides an example to illustrate the method. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.

Low-power and High-speed SCFL-inverter Using Pseudomorphic InGaAs Channel High Electron Mobility Transistors

An SCFL (source coupled FET logic) -based ring oscillator was fabricated with pseudomorphic InGaAs channel high electron mobility transistors (HEMTs) with an extrinsic transconductance of 1.96S/mm. A low power consumption of 26.9mW/gate was obtained for the SCFL inverter along with a propagation delay time of 5.08ps/gate. Low-power operation without sacrificing the propagation delay time is possible because of the low knee voltage of less than 0.3V and the high threshold voltage of near zero volts of a HEMT. These results demonstrate the possibility of the large-scale integration of HEMTs using low-power and high-speed circuit configurations.

Ultra-low power source coupled FET logic gate configurationin GaAs MESFET technology

A source coupled FET logic gate configuration is proposed for achieving high speed and low power dissipation. A frequency of 2.4 GHz has been achieved, based on measurements on a divide-by-20 frequency divider, dissipating only 12 mW from a single 2 V power supply. The performance of the gate in terms of speed is comparable to that of the previously reported high speed source coupled FET logic while dissipating a fraction of the power.

Ultra-high-speed distributed selector IC usingGaAs MESFETs

A novel distributed digital selector circuit is proposed. The circuit comprises eight stages of series-gated source coupled FET logic (SCFL) selector cell units, and can be directly connected to an SCFL interface. The integrated circuit (IC) fabricated with 0.16 µm GaAs MESFETs exhibited clear eye-openings at 70 Gbit/s, a much higher bit rate than that of conventional selector ICs based on a lumped-element circuit design.

55 GHz dynamic frequency divider IC

A divide-by-two dynamic frequency divider based on enhancement and depletion 0.2 µm gate length pseudomorphic AlGaAs/InGaAs-HEMTs (fT = 68 GHz and 60 GHz) was designed and fabricated. High-speed operation up to 55 GHz has been measured. The circuit is based on source-coupled FET logic and has single-ended input and complementary outputs to ground. The power consumption is 300 mW using two supply voltages of 4 and –2.5 V.

Over-60-GHz design technology for an SCFL dynamic frequency divider using InP-based HEMTs

A toggle operation of 39-63.5 GHz without tuning has been achieved by a digital dynamic frequency divider (DFD). The DFD employs a pair of clocked inverters (CIs) with source-coupled FET logic (SCFL) and uses 0.1-/spl mu/m-gate InAlAs/InGaAs/InP high electron-mobility transistors (HEMTs) of good uniformity and high performance. On a 2-in wafer, the frequency divider showed a maximum toggle frequency (f/sub tog,max/) of 59.1/spl plusmn/3.3 GHz and a fabrication yield of 89%. This is the highest operation frequency ever reported for a broad-band digital frequency divider. Comparison of the DFD and the static frequency divider (SFD) showed that the ratio of f/sub tog,max/ for the DFD to that for the SFD is much higher than the value expected from the linear-response theory. The comparison also showed that the ratio of the measured f/sub tog,max/ for the DFD to that for the SFD is 1.7, in contrast with the value of two expected from the circuit simulation. Delay-time analysis revealed that this 15% decrease of the ratio is due to the transmission delay of interconnections and charging time for stray capacitance.

Low power 20 Gbit/s data decision and 17 GHz staticfrequency divider ICs with 1.5 V supply voltage

A data decision and a static frequency divider in source coupled FET logic with a supply voltage of 1.5 V have been designed and fabricated. Both circuits, using 0.2 /spl mu/m gate length enhancement and depletion AlGaAs-GaAs HEMTs (f/sub T/=60/55 GHz), operate up to 20 Gbit/s and 17 GHz. The power consumption is 24 and 21 mW for the data decision circuit and the static frequency divider together with the output buffer, respectively.

A 0-to-40-GHz direct-coupled distributed baseband amplifier IC with SCFL interface

We have developed a distributed baseband amplifier IC with a distributed source-coupled FET logic (SCFL) level transformer. The amplifier and the SCFL level transformer are directly coupled by a distributed level-shift circuit. The amplifier incorporates our new loss-compensation circuit to improve high-frequency performance. The IC, which was fabricated using commercially-available GaAs MESFET's has a gain of 5 dB and a 0-to-41-GHz bandwidth. It can also output a 40-Gbit/s pulse waveform on the SCFL logic level, so it can be directly coupled to an SCFL logic circuit. This is the highest performance among all reported GaAs MESFET baseband amplifiers with an SCFL interface.

Direct-coupled distributed baseband amplifier IC's for 40-Gb/s optical communication

We have developed GaAs MESFET baseband amplifiers using novel distributed amplification schemes. The key feature of their design is a direct coupling architecture employing two kinds of new distributed DC transformers. One is a distributed level-shift circuit and the other is a distributed source coupled FET logic (SCFL) level transformer. A two-stage distributed amplifier IC cascaded with the distributed level-shift circuit has a gain of 17 dB with a 0-to-30 GHz bandwidth. This is the best performance so far among all reported GaAs MESFET baseband amplifier ICs. A distributed baseband amplifier IC with the distributed SCFL level transformer connected by another distributed level-shift circuit also has a 0-to-30 GHz bandwidth with a gain of 7 dB. This is the first IC with an SCFL interface to have such broad-band characteristics.

Characterization and design of GaAs SCFL latched comparators based on improved linearized models

This brief presents characterization and design considerations of high-speed and high-precision GaAs latched comparators consisting of source coupled FET logic (SCFL) flip flops. In order to characterize the comparators, linearized equivalent circuit models are improved for the SCFL flip flops. Based on the models, critical design parameters such as recovery time, regeneration time and input voltage sensitivity are determined for the comparators. Circuit configurations for increasing circuit speed and accuracy are characterized and compared. One comparator is optimized and implemented in a 0.5 /spl mu/m GaAs E/D HEMT technology. Measurement results demonstrate the implemented comparator achieves an average voltage sensitivity of 11.5 mV at low frequencies and an optimal voltage sensitivity of 10.0 mV at an input signal frequency of 2 GHz and a clock frequency of 4 GHz. Predicted voltage sensitivities are also verified to be in good agreement with the measured results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analytical delay expression for source-coupled FET logic (SCFL) inverters

An analytical delay expression for SCFL inverters is proposed based on a transfer function method. Good agreement is obtained between the measured and calculated propagation delays for an SCFL inverter with 0.2-/spl mu/m gate-length GaAs MESFETs. >

A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WN/sub x//W-gate GaAs MESFET's

An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN/sub x//W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz. >

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50- Omega /5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1- mu m gate-length (F/sub tau /=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil*109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10/sup -14/ BER.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A gigasample/second 5-b ADC with on-chip track and hold based on an industrial 1 mu m GaAs MESFET E/D process

To enhance the dynamic accuracy of high-speed A/D conversion, a 5-b flash converter with on-chip track and hold circuitry (T&H) was developed. The design is based on TriQuint's commercial 1 mu m GaAs E/D MESFET process. Dynamic characterization was performed up to 1 gigasample/second (GS/s). An accuracy of 4.4 effective bits even at 1 GS/s with full Nyquist input was achieved. A comparison showing the accuracy with T&H in operation and in tracking-only mode is given. The outstanding performance is due to a carefully designed and the use of differential source-coupled FET logic (SCFL) in the converter. >

Digital GaAs FET versus Si FET gate delay as predicted from the electron velocity

A FET model that takes into account the effective saturation velocity (including the effect of velocity overshoot), fringing capacitance, and source resistance is discussed. The model is applied to identical differential source-coupled FET logic gates in both GaAs and Si. The simulated gate delay of the Si logic gate is about 2.6 times that of the GaAs gate, thus refuting the common hypothesis that GaAs gate, thus refuting the common hypothesis that GaAs and Si delays should be about equal because their equilibrium saturated electron velocities are about equal. >

20 Gbit/s 2:1 multiplexer using 0.3 μm gate length double pulse doped quantum well GaAs/AlGaAs transistors

A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3μm gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The output level can be varied between +1 V an -1 V. Comparison between simulation and measurement shows very good agreement.

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100 degrees C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100 degrees C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>