Chip Scale Package Solder Joint Research Articles

Comparison of results from empirical ALT test to CAE simulation for wireless clients

PurposeThe purpose of this paper is to investigate how to reduce the time and cost required to conduct reliability testing. With increasing competition in the electronics industry and reduction in product life cycles, it is essential to diminish the time required for new product development and thus time to market.Design/methodology/approachThis study conducts empirical sample test for wireless card and analyzes the fatigue life through finite element modeling (FEM). Simulation results are compared to the data collected from a temperature cycling test under conditions of −40°C to 150°C and −40°C to 100°C.FindingsAssuming that the results of product lifetime from empirical sample test and software simulation exhibit a linear relationship, a “scale factor” should exist for any given product structure, process condition and materials composition scenario. The scale factors were found to be approximately 0.1 in both temperature cycling scenarios. Also, the effectiveness of various adhesive dispensing patterns on solder joint reliability is evaluated through software simulation. The L shape adhesive dispensing was proven to effectively enhance the fatigue life of chip scale package solder joints roughly 100‐fold.Originality/valueThe scale factor is used to convert the results from software simulation to empirical sample test for a given set of processing environments and materials. This helps to reduce the time and cost required to conduct reliability testing.

Effects of isothermal aging and temperature–humidity treatment of substrate on joint reliability of Sn–3.0Ag–0.5Cu/OSP-finished Cu CSP solder joint

This study examined the effects of isothermal aging and temperature–humidity (TH) treatment of substrate on the joint reliability of a Sn–3.0Ag–0.5Cu (wt.%)/organic solderability preservative (OSP)-finished Cu solder joint. Two types of OSP-finished chip-scale-package (CSP) substrates were used, those subjected and not subjected to the TH test. This study revealed an association between the interfacial reaction behaviors, void formation and mechanical reliability of the solder joint. Many voids were formed at the interface of the OSP-finished Cu joint subjected to the TH test. These voids were caused by the oxidation of the OSP-finished Cu substrate during the TH test. In the shear tests, the shear force of the joint with the substrate not subjected to the TH test was slightly higher than that with the TH test. The mechanical reliability of the solder joint was degraded by voids at the interface.

The effects of surface finish on the reliability of lead free and tin lead chip scale package solder joints

PurposeThe effects of thermal fatigue and printed circuit board (PCB) surface finish on the pull strength, failure modes and reliability of chip scale package (CSP) solder joints were investigated.Design/methodology/approachMechanical pull test, metallographic examination and electrical measurement were used. Tin lead (Sn‐Pb) and lead free (Sn‐Ag‐Cu) alloys were used with Au/Ni and organic solderability preservative (OSP) surface finishes.FindingsThe experimental results showed that the pull strength of the Sn‐Ag‐Cu/(Au/Ni) solder joint did not change noticeably with an increasing number of thermal cycles. However, the pull strength of the Sn‐Pb/(Au/Ni) solder joints drastically degraded and that of the Sn‐Ag‐Cu/OSP and Sn‐Pb/OSP solder joints slightly decreased during thermal cycling. For both Sn‐Ag‐Cu and Sn‐Pb alloys, the solder joint fracture of as‐soldered samples was the main failure mode when an Au/Ni surface finish was used. For the Sn‐Ag‐Cu/(Au/Ni) and Sn‐Ag‐Cu/OSP solder joints, the proportion of component trace tearing considerably decreased, whereas that of PCB trace tearing considerably increased, during thermal cycling. The Weibull lifetimes of the solder joints were increasingly longer in the order of Sn‐Pb/(Au/Ni), Sn‐Pb/OSP, Sn‐Ag‐Cu/OSP, and Sn‐Ag‐Cu/(Au/Ni).Research limitations/implicationsThis was not an exhaustive study and all of the findings are for lead free and tin lead CSP solder joints, which perhaps limits the usefulness of the results elsewhere.Practical implicationsA very useful source of information and impartial advice for engineers planning to conduct a switch from tin lead to lead free technology in their production lines.Originality/valueThis paper fulfils an identified information/resources need and offers practical help to an engineer starting out on an engineering development.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

Ceramic chip scale package solder joint reliability

As part of a programme of characterisation of interconnection technologies for computer server products the present investigation was conducted to determine the attachment integrity and long‐term reliability of resistor network ceramic Chip Scale Package (CSP) solder joints. Accelerated thermal cycling with electrical continuity monitoring of the solder joints was used to determine reliability. The thermal cycling was combined with metallographic examination of appropriate solder joints to evaluate the failure modes and to corroborate the failure thresholds. The measured reliability for the CSP solder joints was 1,027 thermal cycles. This implied an estimated minimum lifetime of 7.8 years for the product in a worst‐case field use. The reliability was virtually unaffected by the solder joint pad size and geometry on the board. All fatigue failed solder joints exhibited similar failure modes.

Elastic, elastic‐plastic and creep analyses of wafer level chip scale package solder joints on microvia build‐up printed circuit boards

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

Growth kinetics of intermetallic compounds in chip scale package solder joint

Department of Electronic Engineering, and *Department of Physics and Materials Science,City University of Hong Kong, Hong Kong, People’s Republic of China(Received May 18, 2000)(Accepted in revised form August 18, 2000)Keywords: Solder joint; Intermetallic; Aging; Kinetics; FatigueIntroductionAs the trend in requirements of electronic packaging is toward higher I/O, greater performance, higherdensity, and lighter weight, the use of area array packaging technology is expected to increase. The typeof packaging, such as ball grid array (BGA), chip scale package (CSP), and Flip Chip, provides theultimate in high I/O-density and count with superior electrical performance, and very small size. Themechanical properties of solder joint are recognized as one of the critical factors that determine theirreliability and lifetime [1–5]. During soldering, the formation of intermetallic compounds (IMCs) atsolder/substrate interface is inevitable and ensures a good metallurgical bond. However, during storageand field service, the growth of IMCs will influence the strength of solder joints and result inmechanical failure of the joints [6–10]. Our recent research result shows that the fatigue lifetime ofsolder joint decreases linearly with the increasing square root of IMCs layer thickness [11]. Since theintermetallic is responsible for the solder joint failures, attention has to be paid to the effect of IMCsgrowth on the lifetime and reliability of microelectronic assemblies.This paper discusses the Ni-Sn/Cu-Sn IMCs layer growth kinetics in the joint soldered on platedAu/Ni FR-4 printed circuit board (PCB), which is one of the most commonly used substrate for finepitch area array packaging. The kinetic model describing and predicting the IMC thickness can be usedto estimate the solder joint reliability and lifetime, according the relationship of the IMC thickness withvibration fatigue failure and cyclic bend fatigue.Experimental ProceduresIn this experiment, the chip scale package CSP46-T.75 with Sn/Pb-eutectic solder ball was placed andsoldered on FR-4 printed circuit boards using a high-speed flexible mounter (CASIO YCM-5500V) anda 5-zone N

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We developed a highly reliable fan-out-type chip scale package (CSP) for a microcomputer or an ASIC (Application Specific IC) . We found that the solder joint reliability of the CSP under temperature cycling is equal to that of a quad flat package (QFP) and that its mechanical strength (determined from a board-bending test) is much higher than that of a QFP. The fatigue life of a Sn-Ag-Cu lead-free CSP solder joint determined from a cyclic board-bending test is almost equal to that of a Sn-37Pb CSP solder joint. Moreover, compared to a QFP, the occupied area of a CSP is decreased by 75% and its weight is decreased by 90%.

Chip Scale Package Solder Joint Reliability Modeling and Material Characterization.

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on the results of modeling. CSPs with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperature encountered in typical package assembly and die attach processes. Also, lead free solder and 2P versus 3P Weibull distributions are discussed. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability performance results of the μBGA packages, the lead free solder creep, and the 3P Weibull distribution.

Chip Scale Package (CSP) solder joint reliability and modeling

Abstract A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB). The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2-D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. A viscoelastic constitutive model was used for molding compound. Finite element models, incorporating the viscoplastic flow and evolution equations for solder and the viscoelastic equations for molding compound, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless Lead-on-Chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints while a dwell time in excess of 10 min per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between the experiment and the model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatique life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.