Solder Fatigue Model Research Articles

A Physics-of-Failure Investigation of Flip Chip Reliability Based on Lead-Free Solder Fatigue Modeling

Solder fatigue failure is one of the primary wear out failure mechanisms limiting reliability in microelectronics flip chip packaging. Solder fatigue failure occurs when a crack initiates and subsequently propagates through the entirety of the solder joint causing an electrical open. Crack initiation and propagation within a solder joint is caused by a cyclic application of stress, typically induced by exposure to temperature cycle excursions. Understanding the relationship between thermal cycling during product use and the accelerated thermal cycles used for testing is critical for predicting device reliability. MIL-PRF-38535 is the guiding aerospace and high reliability General Specification for Integrated Circuits (Microcircuits) Manufacturing that defines manufacturing, qualification and certification requirements for products to be listed on the Defense Logistic Agency’s (DLA) Qualified Manufacturer Listing (QML). Revision M of this standard, targeted for release in 2022, for the first time includes the use of lead-free solder alloys and organic substrates in the manufacturing of QML flip chip products. Hence there is a strong need to understand the physics-of-failure (PoF) concerning solder fatigue of lead-free flip chip assemblies. This paper demonstrates how finite element modeling can be used to predict solder fatigue for flip chip package assemblies. The authors have leveraged fatigue lives measured for different flip chip daisy chain package configurations, as well as fatigue lives defined and available in published papers. The authors then use the resulting lead-free solder fatigue model to perform parametric studies looking at the impact of different die sizes, underfill material properties, and package substrate materials. Comparisons are also made between eutectic Sn/Pb and lead-free fatigue life predictions. In addition, the authors demonstrate how solder fatigue predictions can be de-rated to use conditions in order to make reliability assessments for flip chip package assemblies. This ultimately leads to a better understanding of the impact of solder alloy and material selection on the mission life of aerospace and high reliability products that fall under the changes introduced in MIL-PRF-38535 Revision M.

Design of BGA Assemblies with Enhanced Thermal Cycle Capability Using Solder Coated Polymer Balls

Abstract Solder coated polymer balls have been successfully employed for attaching packages to circuit boards with minimum standoff height, while accommodating large mismatches in thermal expansion coefficients. Dramatic improvements in temperature cycling performance are often realized by using them in place of solid solder balls, with five-fold increases in mean cycles to failure reported by a number of investigators. The sales literature, provided by suppliers of solder coated solder balls, attribute this superior temperature cycling performance to the soft, compliant polymer core of the product. Our study of the mechanics of solder coated polymer balls has revealed that their stiffness is in fact comparable to that of solid solder balls. Their rigidity results from a composite construction in which a nearly incompressible polymer material is surrounded by a copper shell that is not easily deformed from its spherical shape. We have employed finite element analysis and mechanical measurements to obtain load versus deflection curves for both normal compression and shear displacements of solder coated polymer ball connections. The enhanced temperature cycling performance of solder coated polymer ball connections is also derived from their composite construction. A cross-section through one reveals that near the solder pads, the ratio of copper to polymer is quite high, and consequently so is its resistance to shear. At the mid-plane of the connection, the ratio of copper to polymer is low, which minimizes its shear resistance. Thus, when a solder coated polymer ball connection is subjected to a shear load, as in temperature cycling, most of its deformation occurs around its mid-section. By contrast, when a solid solder ball is subjected to a shear load, most of its deformation occurs near its attachment pads, where its cross-sectional area and hence its stiffness are minimal. In either type of attachment, failure occurs when sufficient plastic strain damage accumulates in the solder to initiate a fracture. By distributing its shear strain over its midsection, a solder coated polymer ball minimizes plastic strain in its solder, where as a solder ball concentrates it near its bond pads. We have used finite element analysis to compute the cumulative plastic strain in various solder coated polymer ball assemblies subjected to cyclic shear loading induced by thermal excursions. By combining these results with an Engelmaier solder fatigue model, we predicted mean number of temperature cycles to failure of the solder connections. Our results compare favorably with published experimental data from temperature cycle tests. We have employed this analysis technique to examine how fatigue life is impacted by various connection parameters such as package size, stand-off height and solder composition, as well as those specific to solder coated polymer balls, which include size and mechanical properties of the core and ratios of solder and copper thicknesses to core diameter. Our overall objective is to enable design of complex stacked assemblies of multichip modules that meet customer reliability requirements for various use environments.

Durability of Pb‐free solder between copper interconnect and silicon in photovoltaic cells

AbstractThe thermal cycling durability of large‐area Pb‐free (Sn3.5Ag) solder between silicon semiconductor and copper interconnects in photovoltaic (PV) cells is assessed and compared to benchmark results from Pb‐based (Sn36Pb2Ag) PV cells. Accelerated thermal cycling tests have been conducted on PV cells of both solder compositions, and the increase in series resistance due to interconnect damage has been characterized using in situ dark I–V measurements. Both the Pb‐free and Pb‐based cells show a steep initial rise followed by a steady rate of increase in degradation histories, with the Pb‐free cells showing a more pronounced ‘knee’ in the degradation curves. Extrapolation of the degradation data for both solders suggests that Pb‐free cells are four times more durable than the Pb‐based cells at the test condition. This superior thermal cycling fatigue durability of Pb‐free cells was also confirmed with physics of failure (PoF) analysis, consisting of nonlinear finite element (FE) stress analysis and an energy‐partitioning (E‐P) solder fatigue model. FE models error‐seeded with manufacturing voids in the solder interconnect predicted a significant reduction in the thermal cycling durability with increasing solder void density. However, even the most voided Pb‐free cells modeled are predicted to be twice as durable as void‐free Pb‐based cells, under the accelerated temperature cycle used in the test. The acceleration factor (AF) predicted by the PoF analysis for a typical service environment is three times higher for Pb‐free cells than that for Pb‐based cells. Copyright © 2010 John Wiley & Sons, Ltd.

Reliability Analysis of Lead-Free Solder Castellations

In this paper, the reliability of lead-free solder castellations is considered. The newly developed stress-dependent Engelmaier's solder fatigue model is utilized in this task. Based on this model, it is possible to interpret the thermal cycling test results. A very good agreement between the test results and the lifetime predictions is obtained. Using the lifetime prediction model, optimal solder castellation shape is investigated. Based on the findings, the fatigue life can be improved by up to 30% simply by solder pad length optimization. Further increment in lifetime length can be expected if the solder joint shape is optimized with the help of modeling tools presented here. Understanding how the crack propagates in solder material is vital if optimal lifetime behavior is expected.

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.

Modified Engelmaier’s model taking account of different stress levels

In this paper, the solder fatigue model created by Werner Engelmaier is modified so that it takes better into account the different stress levels the solder material experiences. This is accomplished by replacing the fatigue ductility constant by a correction term that is temperature- excursion- range-dependent. In order to obtain the correction term, the effect of the temperature cycling profile on lifetime is studied. The correction term obtained is package type specific. More compliant plastic packages with a small coefficient of expansion mismatch with the organic printed wiring board are handled separately, and stiff ceramic packages assembled on an organic board – resulting in a large CTE mismatch – are considered as another entity. Correction terms for both lead-free and tin–lead solder materials are given. This is necessary as the creep characteristics of the solders are different. Comparing solder material specific correction terms makes it possible to determine which solder material performs best in a certain environment and a given assembly type. In the case of ceramic packages, the transition where a eutectic tin–lead solder becomes superior to a SnAgCu solder is expected to take place when temperature excursions are smaller than ca. 70 °C. This indicates that although in a highly accelerated stress test, lead-free solders may be inferior compared to tin–lead solders, in the real field environment, the situation may be reversed.

Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages

In this paper, using a recently developed solder fatigue model for wafer level-chip scale package (WL-CSP), we investigated the improvement on solder joint reliability for a 8-bump micro SMD package by enlarging the passivation layer opening at the solder–die interface. The motivation to enlarge the passivation opening is to reduce the severity of the stress concentration caused by the original design, and also to increase the contact area between the solder bump and aluminum bump pad. It was confirmed in the thermal shock test that with the new design, package fatigue life improved by more than 70%. To numerically predict this improvement represents a unique challenge to the modeling. This is because in order to capture the slightest geometrical difference on the order of a few microns between the two designs, the multiple-layer solder-die interface needs to be modeled using extremely fine mesh, while the overall dimensions of the package and the test board are on the order of millimeters. To bridge this tremendous gap in geometry, a single finite element model that incorporates all necessary geometrical details is deemed computationally prohibitive and impractical. In this paper, we applied a global–local modeling scheme that was also suggested by others [1–3]. The global model contains the complete package with much simplified solder–die interface whereas the local model includes only one solder joint, but with detailed solder–die interface. Unlike most global–local models proposed by others, we included time-independent plasticity and temperature-dependent materials in the global model. This greatly improved model correlation accuracy with only moderate increase in run time. Energy-based solder fatigue model was used to correlate the inelastic strain energy with the package fatigue life. In an earlier study [4], we have found that Darveaux’s equations tended to be conservative when applied to the micro SMD, and hence new correlations based on curve-fitting the test data were derived. In this paper, we used the newly derived equation and achieved less than 20% error in N 50 life for both designs, which is on par with Darveaux’s equations when used for BGAs. The analysis also revealed two factors that may account for the life improvement. First, a slight decrease in inelastic energy dissipation after enlarging the passivation opening. Second, the shift of the crack initiation location which leads to longer crack growth length for the new design. The second factor was also independently confirmed by the failure analysis.

Solder Creep-Fatigue Interactions With Flexible Leaded Parts

With flexible leaded parts, the solder-joint failure process involves a complex interplay of creep and fatigue mechanisms. To better understand the role of creep in typical multi-hour cyclic loading conditions, a specialized non-linear finite-element creep simulation computer program has been formulated. The numerical algorithm includes the complete part-lead-solder-PWB system, accounting for strain-rate dependence of creep on applied stress and temperature, and the role of the part-lead dimensions and flexibility that determine the total creep deflection (solder strain range) during stress relaxation. The computer program has been used to explore the effects of various solder creep-fatigue parameters such as lead height and stiffness, thermal-cycle test profile, and part/board differential thermal expansion properties. One of the most interesting findings is the strong presence of unidirectional creep-ratcheting that occurs during thermal cycling due to temperature dominated strain-rate effects. To corroborate the solder fatigue model predictions, a number of carefully controlled thermal-cycle tests have been conducted using special bimetallic test boards.