Solar Cell Processing Steps Research Articles

Wafer‐scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple‐junction solar cells

AbstractGermanium is listed as a critical raw material, and for environmental and economic sustainability reasons, strategies for lower consumption must be implemented. A promising approach is Ge lift‐off concepts, which enable to re‐use the substrate multiple times. Our concept is based on the Ge‐on‐Nothing approach that is the controlled restructuring at high temperature of a macroporous Ge surface, forming a Ge foil weakly attached to its parent wafer. Its suitability as III–V epitaxy seed and support substrate has previously been demonstrated with proof‐of‐concept solar cells. This work focuses on bringing this concept to the next level, by upscaling the detachable area to a full 200‐mm wafer scale, increasing foil thickness for sufficient light absorption in the Ge bottom cell, and improving the control on the strength that is bonding the suspended foil to its parent. By introducing a new high growth‐rate epitaxy process from GeCl4, and by engineering the GeON structure to introduce pillars with ad hoc density and shape, we fabricated P‐type foils with tunable boron doping up to 15 μm in thickness and 11 cm × 11 cm in area, for which the detachment strength could be adapted to the stresses induced by the solar cell process steps. The surface roughness and the electrical and crystal qualities of these foils were inspected by AFM, SIMS, SRP, ECCI, and TEM to check the GeCl4‐based epitaxy conditions and to check that the ad hoc pillars were not introducing any damage. Small‐area triple‐junction lattice‐matched GaInP/GaInAs/Ge solar cells were fabricated on 7‐μm‐thick Ge foils with various pillar densities and on a standard reference Ge wafer. The III–V layer nucleation was virtually the same on both substrates and the solar cells on the GeON foils performed in the same way as the cells on the Ge wafer, albeit a small loss in short‐circuit current and open‐circuit voltage that can be attributed to the thickness reduction and absence of rear‐side passivation. We conclude that it is possible to gain control on the GeON detachability and upscale the concept to areas relevant for the space PV industry, proving that porous germanium is a serious candidate for replacement of bulk Ge wafers in view of a more sustainable multijunction solar cell process.

Lifetime spectroscopy with high spatial resolution based on temperature- and injection dependent photoluminescence imaging

In this paper we present a method for performing temperature- and injection dependent lifetime spectroscopy (TIDLS) with high spatial resolution based on steady state photoluminescence (PL) images taken at a range of excitation intensities and temperatures. The PL lifetime images are calibrated based on temperature dependent photoconductance measurements, thus requiring a minimum of assumptions regarding the temperature dependency of the luminescence signal and detection system. PL image acquisition at varying conditions and subsequent data analysis is automated, allowing for investigations of different samples without the need for excessive operator time. We demonstrate the method by presenting lifetime data and TIDLS analysis from commercial HPMC-Si samples, highlighting the local differences in the recombination properties for high lifetime in-grain areas and lower lifetime areas dominated by dislocation clusters. These regions have been investigated for two etched and passivated neighboring wafers, one in the as-cut state and one where the bulk lifetime had been improved through key solar cell process steps. For the as-cut wafer we find two dominant defects in the low lifetime area, one of which is identified as FeB pairs, with Et = 0.90 ± 0.01 (above the valence band) and k = 0.4 ± 0.1. In the in-grain region of this wafer we also observe two dominating defects, one with an energy level of either 0.28 ± 0.01 eV or 0.74 ± 0.01 eV above the valence band and a k value of 25 ± 1. The other defect is shallow, within ~0.27 eV of the band edge, and could not be further identified with the chosen temperature range. For the wafer that had passed through solar cell processing, we find a clear, overall improvement in the lifetime and a change in the type of dominating defects: We observe that a single, deep defect with 0.35 eV < Et < 0.7 eV and a capture cross section ratio k = 10 ± 1 can fully describe the observed lifetime data in the in-grain area after solar cell processing, whereas two defects are needed to describe the behavior of the lower lifetime regions. One of these defects is also a deep defect with 0.34 eV < Et < 0.69 eV but with a higher k of 25 ± 2, and is thus similar to one of the defects observed in the in-grain region of the as-cut wafer. The other is a shallow defect with Et within 0.21 eV of the band edge. Finally, we show how the method can be used to show interesting new properties of the lifetime maps, including maps of the temperature coefficient of the lifetime, maps of the injection dependence of the lifetime and maps at a constant injection level.

Simulated and measured temperature coefficients in compensated silicon wafers and solar cells

In this paper we perform a thorough investigation of the temperature coefficients of c-Si solar cells and wafers, based on both experimental data and device simulations. Groups of neighboring wafers were selected from different heights of four high performance multicrystalline silicon ingots cast using different dopants concentrations and Si feedstocks; Three different target resistivities of compensated silicon ingots based on Elkem Solar Silicon (ESS®), which are purified through a metallurgical route, and one non-compensated reference ingot. The wafers were processed into Al-BSF and PERCT type solar cells, as well as into lifetime samples subjected to selected solar cell processing steps before being etched down and re-passivated to assess the bulk lifetime of the final cells. Temperature-dependent photoluminescence imaging was used to study the spatial distribution of the carrier lifetime and the temperature coefficient of the lifetime. We observe a beneficial effect of higher doping levels on the temperature coefficients of the short circuit current JSC in PERCT type cells, with the most favorable temperature coefficients are found in the ingot doped to 0.5 Ω-cm. Increasingly beneficial temperature coefficients in JSC is also observed with increasing height in each ingot, which might be attributed to a combination of small variations in the dopant concentrations and to a clear increase in the temperature coefficient of the carrier lifetime with increasing ingot height. The latter point is also in agreement with the changes in the so-called gamma parameter of the open circuit voltage throughout the ingot. To build a more fundamental understanding of the experimental results the temperature dependence of the solar cells was simulated using PC1Dmod6.2. We find that the experimental temperature coefficients of the final cells can be reproduced in device simulations within 8% of and 14% for the VOC and JSC, respectively. The compensation level itself is of minor importance for the cell performance. Instead, the simulations indicate that the observed behavior in the temperature coefficients of the solar cells is mostly explained by differences in the net doping and carrier lifetime of the wafers.

Structural and chemical evolution of the CdS:O window layer during individual CdTe solar cell processing steps

Oxygenated cadmium sulfide (CdS:O) is often used as the n-type window layer in high-performance CdTe heterojunction solar cells. The as-deposited layer prepared by reactive sputtering is XRD amorphous, with a bulk composition of CdS0.8O1.2. Recently it was shown that this layer undergoes significant transformation during device fabrication, but the roles of the individual high temperature processing steps was unclear. In this work high resolution transmission electron microscopy coupled to elemental analysis was used to understand the evolution of the heterojunction region through the individual high temperature fabrication steps of CdTe deposition, CdCl2 activation, and back contact activation. It is found that during CdTe deposition by close spaced sublimation at 600 °C the CdS:O film undergoes recrystallization, accompanied by a significant (∼30%) reduction in thickness. It is observed that oxygen segregates during this step, forming a bi-layer morphology consisting of nanocrystalline CdS adjacent to the tin oxide contact and an oxygen-rich layer adjacent to the CdTe absorber. This bilayer structure is then lost during the 400 °C CdCl2 treatment where the film transforms into a heterogeneous structure with cadmium sulfate clusters distributed randomly throughout the window layer. The thickness of window layer remains essentially unchanged after CdCl2 treatment, but a ∼25 nm graded interfacial layer between CdTe and the window region is formed. Finally, the rapid thermal processing step used to activate the back contact was found to have a negligible impact on the structure or composition of the heterojunction region.

Accuracy of Interstitial Iron Measurements on P-Type Multicrystalline Silicon Blocks by Quasi-Steady-State Photoconductance

A detailed knowledge of the distributions of carrier lifetimes, impurities, and crystal defects in silicon ingots is key for understanding and improving wafer quality, as well as solar cell processing steps. In this work, we have validated the use of the quasi-steady-state photoconductance method on p-type multicrystalline silicon blocks to determine the interstitial iron concentration. The extracted iron concentrations along a silicon block were compared with the interstitial iron concentrations measured on wafers from different heights of an adjacent block. The lifetime measurements were performed on the block before and after flashing to break the iron–boron pairs. The impact of nonuniform carrier profiles during the block measurements on the extraction of the Fe profiles is discussed and quantified based on simulations of the quasi-steady-state measurement conditions. The simulation results reveal a slight error in the extracted interstitial iron concentration along the block. However, this error is generally less than 20% for iron concentrations below 1011 cm–3, which is typical in the central region of an ingot, and in any case, can be corrected for based on the modeling results.

High-Efficiency Multicrystalline Silicon Solar Cells: Potential of n-Type Doping

In this study, we demonstrate the potential of multicrystalline (mc) n-type silicon for the fabrication of highly efficient mc-Si solar cells. High-quality mc n-type silicon wafers are obtained from a research ingot crystallized in a high-purity crucible, using high-purity granular silicon as seed layer in the crucible bottom and high-purity polysilicon feedstock for the block. An mc p-type silicon block crystallized under identical conditions (same seed and feedstock, crucible system, and temperature profiles) serves as reference and enables measurements of the interstitial iron and chromium concentrations by metastable defect imaging. In combination with 2-D simulations for in-diffusion and precipitation of chromium, the limitation of n-type high-performance mc silicon by these metals is assessed after different solar cell processing steps. Material-related efficiency losses are assessed by an “efficiency limiting bulk recombination analysis,” which combines injection-dependent photoluminescence imaging of minority charge carrier diffusion length with PC1D cell simulations. Finally, based on this material, boron-diffused front-junction mc n-type silicon solar cells with a full-area passivated rear contact (TOPCon) are fabricated. The record cell features an efficiency of 19.6%, which is the highest efficiency reported for an mc n-type silicon solar cell.

Efficiency Potential of p- and n-type High Performance Multicrystalline Silicon

Seed-assisted growth of multicrystalline (mc) silicon ingots has led to a significant increase in mc silicon material quality (so called high performance multicrystalline silicon, “HPM Si”) and thus efficiencies of p-type mc silicon solar cells in the past years. Additionally, recent research revealed a high efficiency potential of n-type standard mc silicon due to its large tolerance to many metallic impurities. This suggests a high potential of n-type high performance mc silicon with a low density of dislocation clusters. In this study, the efficiency potential of p- and n-type high performance mc silicon, produced under identical conditions in the same laboratory crystallization furnace, is investigated after different high efficiency solar cell processing steps. The prediction of solar cell efficiencies by an “Efficiency limiting bulk recombination analysis” (ELBA) discloses a very high potential with material related losses of less than 1%abs. compared to the cell limit. In combination witha high efficiency cell concept featuring a full area passivated rear contact (TOPCon), efficiencies exceeding 20% on isotextured n-type HPM samples and close to 22% on samples with an improved texture are predicted. To support these predictions with results on actual devices, solar cells were fabricated. First results on cell level indicate high Voc and Jsc values in the range predicted by ELBA simulations and an efficiency of 19.3%.

Potential Gain in Multicrystalline Silicon Solar Cell Efficiency by n-Type Doping

This study aims for a quantitative investigation of the material limitations and the efficiency potential of an entire multicrystalline (mc) n-type silicon block in comparison with an mc p-type block of the same purity level in order to predict the potential of mc n-type silicon for the industrial production of solar cells. Therefore, two standard mc silicon blocks were crystallized under identical conditions (same high purity feedstock, crucible system, and temperature profiles), only differing in their type of doping. The material quality of wafers along the whole block height is analyzed after different solar cell process steps by photoluminescence imaging of the diffusion length. The bulk recombination related efficiency losses are assessed by an “efficiency limiting bulk recombination analysis (ELBA),” combining injection dependent lifetime images with PC1D cell simulations. The influence of the base resistivity variation along the block is considered in the PC1D cell simulations and backed up by Sentaurus Device simulations. This analysis predicts a significantly higher material-related efficiency potential after typical solar cell processes along the whole block height for mc n-type silicon compared with mc p-type silicon. In addition, the efficiency potential for mc n-type silicon depends less on block position.

Comparative analysis of mechanical properties of Si substrates processed by different routes

AbstractThe purpose of this work is to check the potential of innovative processes for the Si wafers production toward the solar cell industry. Studies have been focused on a comparative analysis of mechanical properties of such wafers, since: (i) reduced wafer strength leads to a high breakage rate during subsequent handling and solar cell processing steps, (ii) cracking of solar cells has become one of the major sources of solar module failure and rejection. Therefore while developing new types of wafer materials and processing, it is essential to assess the mechanical strength of the wafers. Mechanical properties of several innovative Si based substrates are estimated. The bending strength measurements of the silicon wafer are performed using the ring‐on‐ring set‐up coupled with a numerical model to obtain estimate of the fracture stress and the Weibull parameters of the fracture distribution. Results are presented for five different materials: sintered Si powder, standard multi‐crystalline Si, Czochralski monocrystalline Si, and two types of thermal sprayed Si wafers.

Characterization of the interface properties in a-Si : H/c-Si heterostructures by photoluminescence

Photoluminescence measurements on hydrogenated amorphous silicon/crystalline silicon (a-Si : H/c-Si) heterostructures have been used for two aspects of their characterization: the monitoring of the crystalline silicon wafers and of their interface properties after different steps of solar cell processing and the tracking of interface properties on purpose-built symmetrical structures with different amorphous silicon overlayers. The difference in the quasi-Fermi level splittings in these symmetrical structures, determined both experimentally and by numerical modelling, suggests an energetic position of the interface defect distribution with a peak at around 0.7–0.8 eV above the c-Si valence band edge. Numerical modelling is also applied to the structures after solar cell processing steps and consistently tracks the variation in quasi-Fermi level splitting, i.e. excess carrier densities, in the c-Si layer. The agreement in the experimental and simulated open-circuit voltages for the final cell adds confidence to the interface defect parameters determined.

Iron Gettering in CZ Silicon during the Industrial Solar Cell Process

We investigated the impact of using low quality feedstock such as recycled silicon and simplified pulling condition on the performance of CZ silicon solar cells. Groups of wafers carefully chosen from different ingots were analyzed after different solar cell process steps by minority carrier lifetime measurements, by measurements of the interstitial iron content and by measurements of the total impurity content using NAA. Our results show that the main electronic properties of the ingots, namely the carrier lifetime, interstitial iron content and base resistivity are strongly affected by feedstock quality. Surprisingly, high solar cell efficiencies were achieved using highly contaminated silicon. These positive results are due to the beneficial effect of impurity segregation gettering by phosphorous diffusion and aluminum alloying. Post-diffusion gettering by an additional annealing step was demonstrated to enhance the charge carrier lifetime.

Study of process induced variation in the minority carrier lifetime of silicon during solar cells fabrication

A systematic study of the variation in the minority carrier effective lifetime in silicon associated with the different solar cell processing steps in a conventional industrial production line has been carried out using the microwave photoconductive decay (μ-PCD) technique. The solar grade silicon wafers used for this study presented bulk carrier lifetime of ∼10 μs and resistivity 0.5–3 Ω cm. Alkali texturing, phosphorus diffusion using POCl 3, thermal oxide growth for surface passivation, plasma etching for edge isolation, and APCVD of TiO 2 for surface passivation and antireflection coating were the major steps taken into consideration. The results clearly showed that the lifetime increased as the fabrication process proceeds from the bare wafer with the exception of the step associated to plasma edge isolation. The effective lifetime of the bare wafer was 4.04 μs, which increased to 16.67 μs after the antireflection coating and surface passivation with TiO 2. The results of a systematic study of the effective minority carrier lifetime of silicon due to different surface passivation processes are also reported. The results obtained are useful for the design and implementation of proper measures for minority carrier lifetime enhancement during silicon solar cell fabrication at the industrial scale.

Cu(In,Ga)Se&lt;sub&gt;2&lt;/sub&gt; Prepared by a 2 and 3-Stage Hybrid RF-Magnetron Sputtering and Se Evaporation Method: Properties and Solar Cell Performance

The potential of RF-magnetron sputtering to achieve high quality Cu(In,Ga)Se2 (CIGS) thin films and efficient solar cells with the goal of using a single technique for all solar cell processing steps is explored. The end point detection method was adapted to RF-magnetron deposition of CIGS in two- or three stages sputtering process. It allows the control of the final composition of the deposited layers in a reproducible way. The influence of substrate temperature and Ar pressure during the deposition on the surface and crossectional morphology of CIGS films was studied for two and three-stage sputtering process sequence. The solar cells prepared with films deposited by two-stage sputtering nave showed a better performance with maximum efficiency above 8 %.

Processing step-related upgrading of silicon-based solar cells detected by photoluminescence spectroscopy

The aim of this work was to study the effect of solar cell processing steps on the electrical quality of the material, using photoluminescence spectroscopy as a non-contact technique. It was confirmed that consecutive steps in solar cell processing not only lead to electronic quality upgrading in Ribbon and multicrystalline silicon wafers, but also to the introduction of recombining defects. Furthermore, the importance and usefulness of photoluminescence technique on the overall improvement of the substrate material is discussed.

High‐rate deposition of epitaxial layers for efficient low‐temperature thin film epitaxial silicon solar cells

AbstractLow–temperature deposition of Si for thin‐film solar cells has previously been hampered by low deposition rates and low material quality, usually reflected by a low open‐circuit voltage of these solar cells. In contrast, ion‐assisted deposition produces Si films with a minority‐carrier diffusion length of 40 μm, obtained at a record deposition rate of 0.8 μm/min and a deposition temperature of 650°C with a prebake at 810°C. A thin‐film Si solar cell with a 20‐μm‐thick epitaxial layer achieves an open‐circuit voltage of 622 mV and a conversion efficiency of 12.7% without any light trapping structures and without high‐temperature solar cell process steps. Copyright © 2001 John Wiley &amp; Sons, Ltd.