SOI Chips Research Articles

Heterogeneous integration of single InAs/InP quantum dots with the SOI chip using direct bonding.

Quantum information processing with photons in small-footprint and highly integrated silicon-based photonic chips requires incorporating non-classical light sources. In this respect, self-assembled III-V semiconductor quantum dots (QDs) are an attractive solution, however, they must be combined with the silicon platform. Here, by utilizing the large-area direct bonding technique, we demonstrate the hybridization of InP and SOI chips, which allows for coupling single photons to the SOI chip interior, offering cost-effective scalability in setting up a multi-source environment for quantum photonic chips. We fabricate devices consisting of self-assembled InAs QDs embedded in the tapered InP waveguide (WG) positioned over the SOI-defined Si WG. Focusing on devices generating light in the telecom C-band compatible with the low-loss optical fiber networks, we demonstrate the light coupling between InP and SOI platforms by observing photons outcoupled at the InP-made circular Bragg grating outcoupler fabricated at the end of an 80 µm-long Si WG, and at the cleaved edge of the Si WG. Finally, for a device with suppressed multi-photon generation events exhibiting 80% single photon generation purity, we measure the photon number outcoupled at the cleaved facet of the Si WG. We estimate the directional on-chip photon coupling between the source and the Si WG to 5.1%.

Computational Study of the Coupling Performances for a Long-Distance Vertical Grating Coupler

We present a high-efficiency silicon grating coupler design based on a left–right mirror-symmetric grating and a metal mirror. The coupler achieves nearly perfect 90-degree vertical coupling. When two SOI chips are placed face to face with a vertical working distance of 50 μm, the chip-to-chip interlayer coupling efficiency reaches as high as 96%. When the vertical working distance ranges from 45 μm to 55 μm, the coupling loss remains below 1 dB. We also verified the effectiveness of our designed vertical coupler through 3D FDTD full-model simulation. The results demonstrate that our proposed vertical coupling structure represents a high-efficiency solution for 3D optical interconnects. The integration of multiple photonic chips in a 3D package with vertical optical and electrical interconnects is also feasible in the foreseeable future.

Design of Low-Power Active Tags for Operation With 77–81-GHz FMCW Radar

The system and transistor-level design of low-power millimeter wave (mm-wave) active tags in silicon is discussed in detail. Two active mm-wave tags with identical system architecture, padframe, and chip size were designed and fabricated in 55-nm SiGe BiCMOS and 45-nm SOI CMOS technologies, respectively. They feature a three-stage low-noise amplifier (LNA), a wake-up detector, a BPSK modulator, and two variable gain output stages, each driving a separate transmit antenna in antiphase. The wake-up detector can be used to switch OFF all the blocks except for the LNA and detector, thus further reducing power consumption. The measured performance of the SiGe and SOI chips is remarkably similar: 19- and 20-dB gain, 9- and 8-dB noise figure, and 25-/10.8-mW (active/idle) and 18-mW power consumption, respectively. The SiGe tag was flip-chip-mounted on a mini-PCB with one receive and two transmit antennas for system level functionality tests carried out over a distance of 5 m. The SiGe-tag wake-up sensitivity was verified to be −62 dBm, in excellent agreement with simulation results.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Recess Photomask Contact Lithography and the fabrication of coupled silicon photonic and plasmonic waveguide switches

A novel lithographic method is presented, based on the use of a mask aligner in the contact mode with a modified photomask, the so-called recess photomask; its goal is the printing of submicron-sized patterns into deep cavities of a chip, which is not manageable with conventional contact lithography. The photomask (initially a standard photomask) is etched in designated sections in order to obtain a surface nearly conformal to the topography of the wafer to be patterned and allowing to maintain the ultimate resolution of UV mask aligners in the contact mode, down to ∼0.5μm critical dimension at 250nm wavelength in spite of the difficult topography of the chip. The technique is successfully applied to the integration of polymer and gold plasmonic structures in silicon photonic SOI chips with 1.9μm deep cavities intended to accommodate the plasmonic waveguide switching technology. In this specific application, coupling of silicon photonic waveguides with small-footprint plasmonic waveguides can assure ultrafast and low-power electrically-driven thermo-optical switching. The method is generic as it can be applied to any pre-existing resist process and has no theoretical recess depth limit. It is potentially widely applicable to emerging technologies in fields including optoelectronic and integrated optical communications devices, but also potentially MEMS and MOEMS.

Design and fabrication of SOI micro-ring resonators based on sub-wavelength grating waveguides.

Standard silicon photonic strip waveguides offer a high intrinsic refractive index contrast; this permits strong light confinement, leading to compact bends, which in turn facilitates the fabrication of devices with small footprints. Sub-wavelength grating (SWG) based waveguides can allow the fabrication of low loss devices with specific, engineered optical properties. The combination of SWG waveguides with optical micro-resonators can offer the possibility of achieving resonators with properties different from the traditional SOI rings. One important property that SWG rings can offer is decreased light confinement in the waveguide core; this improves the resonator's sensitivity to changes in the cladding refractive index, making the rings ideal for refractive index sensing applications. In this paper, we present the design and experimental characterization of SWG based rings realized on SOI chips without upper cladding (permitting their use as sensors). The fabricated rings offer quality factors in the range of ~1k-6k, depending on SWG parameters. Based on the comparison of experimental and simulated data we expect sensitivities exceeding 383 nm/RIU in water and 270 nm/RIU in air, showing excellent potential for use in sensing applications.

Optical power monitors in Ge monolithically integrated on SOI chips

We report on the fabrication and operation of optical power monitors monolithically integrated on silicon-on-insulator optical chips. The devices consist of near-infrared waveguide pn heterojunction photodiodes in evaporated germanium. The low temperature growth of Ge is compatible with silicon waveguide technology. The photodetectors exhibit typical responsivities of 10–30 mA/W; the power monitors are used with front-end trans-impedance amplifiers based on commercially available operational amplifiers and can operate with optical signals as small as 10 nW, with errors below 0.2% and 2% at 1 and 0.1 μW, respectively.

Near-Infrared Ge-on-Si Power Monitors Monolithically Integrated on SOI Chips

We realize and test power monitors monolithically integrated on silicon-on-insulator optical chips. The devices consist of near-infrared waveguide photodetectors in evaporated germanium with front-end transimpedance amplifiers. The power monitors operate with signals as small as 10 nW, with errors below 0.2% and 2% at 1 and 0.1 ¿W , respectively.

EVALUATION OF RESONATING CHANNEL TRANSISTOR IN SOI WAFER

International Journal of Computational Engineering ScienceVol. 04, No. 03, pp. 711-714 (2003) Poster PapersNo AccessEVALUATION OF RESONATING CHANNEL TRANSISTOR IN SOI WAFERS. MYLLYMAKI, E. RISTOLAINEN, P. HEINO, A. LEHTO, and K. VARJONENS. MYLLYMAKITampere University Technology, Finland Search for more papers by this author , E. RISTOLAINENTampere University Technology, Finland Search for more papers by this author , P. HEINOTampere University Technology, Finland Search for more papers by this author , A. LEHTOTampere University Technology, Finland Search for more papers by this author , and K. VARJONENTampere University Technology, Finland Search for more papers by this author https://doi.org/10.1142/S1465876303002118Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractA new type of oscillating transistor structure has been developed in thin film SOI applications.The oscillator's mechanical resonator has circular shape and vertical vibration. By using conventional SOI chips with other electronics it possible to add this resonator in same structure without complex process steps. The oscillating transistor can be used primarily in low frequencies (MHz). The component has one electrostatically driven electrode and two electrodes for drain and source parts. By using this component, the transistor can be driven electrostatically. It can have higher voltage current aplification -ratio than conventional transistor because of mechanic impact. For filter solutions coupling rods are not needed. The structure have been measured Q-value of 700 at 3,3MHz in normal room conditionsKeywords:SOItransistorresonatoroscillatorMEMS References C. T.-C. Nguyen, Transceiver Front-End Architectures Using Vibrating Micromechanical Signal Precessors, Dig. of Papers, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Sept. 12-14 (2001) 23-32 . Google Scholar S. Yoel, F. Ayazi, The HARPSS process for fabrication of nano-precision silicon electromechanical resonators, 1st IEEE Conference on Nanotechnology, December (2001) 489-494 . Google Scholar H.C. Nathanson, et al., The Resonant Gate Transistor, IEEE Trans. Electron Devices, March, vol. 14, no. 3 (1967) 117-133 . Google Scholar FiguresReferencesRelatedDetails Recommended Vol. 04, No. 03 Metrics History KeywordsSOItransistorresonatoroscillatorMEMSPDF download

Silicon-on-lnsulator Technology

Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.