Software-only System Research Articles

WITHDRAWN: Embedded Hardware System and Sensor Robot Used In Goal Tracking Technology Of Sports Football Goalkeeper

ABSTRACT The purpose of the software-only system built into the hardware of the design is called embedded systems. The system is maybe a stand-alone system or a larger system. Software is usually built into the memory module. It does not require any auxiliary storage device in the computer. Telecommunications, smart cards, missiles, computer networks, digital consumer electronics, and satellites are part of the sensor's robot used in embedded systems. In embedded systems, hardware platforms need to interact with various real-time input and output or variable. In the previous method Principal Component Analysis (PCA) Algorithm and Independent Component Analysis (ICA), several countries encourage football practice for rehabilitation and social inclusion purposes. For visually impaired people, football is purely sound-based, where the ball and the players are constantly emitting sounds for localization purposes in the field. The proposed Support Vector Machine (SVM) algorithm Embedded Hardware System and Sensor Robot Used in Goal Tracking Technology of Sports Football Goalkeeper Functions The electronics' goal, the position and the ball is by returning the feedback based on the sound that are affecting the location. It is to design the four functions for training. The system has confirmed the volunteers from the Chilean national football team.

Validation of a novel stand-alone software tool for image guided cardiac catheter therapy

Comparison of the targeting accuracy of a new software method for MRI-fluoroscopy guided endomyocardial interventions with a clinically available 3D endocardial electromechanical mapping system. The new CARTBox2 software enables therapy target selection based on infarction transmurality and local myocardial wall thickness deduced from preoperative MRI scans. The selected targets are stored in standard DICOM datasets. Fusion of these datasets with live fluoroscopy enables real-time visualization of MRI defined targets during fluoroscopy guided interventions without the need for external hardware. In ten pigs (60–75 kg), late gadolinium enhanced (LGE) MRI scans were performed 4 weeks after a 90-min LAD occlusion. Subsequently, 10–16 targeted fluorescent biomaterial injections were delivered in the infarct border zone (IBZ) using either the NOGA 3D-mapping system or CARTBox2. The primary endpoint was the distance of the injections to the IBZ on histology. Secondary endpoints were total procedure time, fluoroscopy time and dose, and the number of ventricular arrhythmias. The average distance of the injections to the IBZ was similar for CARTBox2 (0.5 ± 3.2 mm) and NOGA (− 0.7 ± 2.2 mm; p = 0.52). Injection procedures with CARTBox2 and NOGA required 69 ± 12 and 60 ± 17 min, respectively (p = 0.36). The required endocardial mapping procedure with NOGA prior to injections, leads to a significantly longer total procedure time (p < 0.001) with NOGA. Fluoroscopy time with NOGA (18.7 ± 11.0 min) was significantly lower than with CARTBox2 (43.4 ± 6.5 min; p = 0.0003). Procedures with CARTBox2 show a trend towards less ventricular arrhythmias compared to NOGA. CARTBox2 is an accurate and fast software-only system to facilitate cardiac catheter therapy based on gold standard MRI imaging and live fluoroscopy.

A Lightweight System for Detecting and Tolerating Concurrency Bugs

Along with the prevalence of multi-threaded programs, concurrency bugs have become one of the most important sources of software bugs. Even worse, due to the non-deterministic nature of concurrency bugs, these bugs are both difficult to detect and fix even after the detection. As a result, it is highly desired to develop an all-around approach that is able to not only detect them during the testing phase but also tolerate undetected bugs during production runs. However, existing bug-detecting and bug-tolerating tools are usually either 1) constrained in types of bugs they can handle or 2) requiring specific hardware supports for achieving an acceptable overhead. In this paper, we present a novel program invariant, name Anticipating Invariant ( Ai ), that can detect most types of concurrency bugs. More importantly, Ai can be used to anticipate many concurrency bugs before any irreversible changes have been made. Thus it enables us to develop a software-only system that is able to forestall failures with a simple thread stalling technique, which does not rely on execution roll-back and hence has good performance. Experiments with 35 real-world concurrency bugs demonstrate that Ai is capable of detecting and tolerating many important types of concurrency bugs, including both atomicity and order violations. It has also exposed two new bugs (confirmed by developers) that were never reported before in the literature. Performance evaluation with 6 representative parallel programs shows that Ai incurs negligible overhead ( $ ) for many nontrivial desktop and server applications.

CEO: A context event only indoor localization technique for AAL

Ambient Assisted Living applications are deployed in smart environments that provide some basic services, a typical example being user localization. AAL applications generally have low accuracy requirements for indoor localization; this opens the opportunity for parasitizing the existing smart environment infrastructure without adding dedicated positioning sensors. In this scenario, one can exploit simple binary sensors that are usually present in the smart environment, such as light and appliance switches or intrusion detection sensors, to obtain a rough estimate of the position of the user. This application is device-free, meaning that the user is not required to carry any device in order to be localized. In this paper we present CEO, a software-only system which we evaluate along the technical guidelines of the EvAAL competition. While the localization performance of CEO is lower with respect to most EvAAL competitors of past editions, it has the benefit of being non-intrusive, easy to install and perfectly compatible with other software systems: these characteristics would made it a potentially significant EvAAL competitor. While developing CEO, we only exploited the definition of the EvAAL competition environment as it was presented to competitors. The only inputs to CEO are the context events generated during the competition, which in 2012 and 2013 were limited to pressing light switches and using a stationary bicycle. We compare the performance of CEO against the results of those editions of EvAAL and show how it can be used to easily improve the performance of any EvAAL competitor.

Hardware Accelerator Approach Towards Efficient Biometric Cryptosystems for Network Security

Protecting data and its communication is a critical part of the modern network. The science of protecting data, known as cryptography, uses secret keys to encrypt data in a format that is not easily decipherable. However, most commonly secure logons for a workstation connected to a network use passwords to perform user authentication. These passwords are a weak link in the security chain, and are a common point of attack on cryptography schemes. One alternative to password usage for network security is to use a person’s physical characteristics to verify who the person is and unlock the data correspondingly. This study focuses on the Cambridge biometric cryptosystem, a system for performing user authentication based on a user’s iris data. The implementation of this system expanded from a single-core software-only system to a collaborative system consisting of a single core and a hardware accelerator. The experiment takes place on a Xilinx Zynq-7000 All Programmable SoC. Software implementation is performed on one of the embedded ARM A9 cores while hardware implementation makes use of the programmable logic. Our hardware acceleration produced a speedup of 2.2X while reducing energy usage to 47.5 % of its original value for the combined enrolment and verification process. These results are also compared to a many-core acceleration of the same system, providing an analysis of different acceleration methods.

Paraprox

Approximate computing is an approach where reduced accuracy of results is traded off for increased speed, throughput, or both. Loss of accuracy is not permissible in all computing domains, but there are a growing number of data-intensive domains where the output of programs need not be perfectly correct to provide useful results or even noticeable differences to the end user. These soft domains include multimedia processing, machine learning, and data mining/analysis. An important challenge with approximate computing is transparency to insulate both software and hardware developers from the time, cost, and difficulty of using approximation. This paper proposes a software-only system, Paraprox, for realizing transparent approximation of data-parallel programs that operates on commodity hardware systems. Paraprox starts with a data-parallel kernel implemented using OpenCL or CUDA and creates a parameterized approximate kernel that is tuned at runtime to maximize performance subject to a target output quality (TOQ) that is supplied by the user. Approximate kernels are created by recognizing common computation idioms found in data-parallel programs (e.g., Map, Scatter/Gather, Reduction, Scan, Stencil, and Partition) and substituting approximate implementations in their place. Across a set of 13 soft data-parallel applications with at most 10% quality degradation, Paraprox yields an average performance gain of 2.7x on a NVIDIA GTX 560 GPU and 2.5x on an Intel Core i7 quad-core processor compared to accurate execution on each platform.

Paraprox

Approximate computing is an approach where reduced accuracy of results is traded off for increased speed, throughput, or both. Loss of accuracy is not permissible in all computing domains, but there are a growing number of data-intensive domains where the output of programs need not be perfectly correct to provide useful results or even noticeable differences to the end user. These soft domains include multimedia processing, machine learning, and data mining/analysis. An important challenge with approximate computing is transparency to insulate both software and hardware developers from the time, cost, and difficulty of using approximation. This paper proposes a software-only system, Paraprox, for realizing transparent approximation of data-parallel programs that operates on commodity hardware systems. Paraprox starts with a data-parallel kernel implemented using OpenCL or CUDA and creates a parameterized approximate kernel that is tuned at runtime to maximize performance subject to a target output quality (TOQ) that is supplied by the user. Approximate kernels are created by recognizing common computation idioms found in data-parallel programs (e.g., Map, Scatter/Gather, Reduction, Scan, Stencil, and Partition) and substituting approximate implementations in their place. Across a set of 13 soft data-parallel applications with at most 10% quality degradation, Paraprox yields an average performance gain of 2.7x on a NVIDIA GTX 560 GPU and 2.5x on an Intel Core i7 quad-core processor compared to accurate execution on each platform.

Kendo

Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded applications, causes significant challenges for parallel programmers by hindering their ability to create parallel applications with repeatable results. As a consequence, parallel applications are significantly harder to debug, test, and maintain than sequential programs. This paper introduces Kendo: a new software-only system that provides deterministic multithreading of parallel applications. Kendo enforces a deterministic interleaving of lock acquisitions and specially declared non-protected reads through a novel dynamically load-balanced deterministic scheduling algorithm. The algorithm tracks the progress of each thread using performance counters to construct a deterministic logical time that is used to compute an interleaving of shared data accesses that is both deterministic and provides good load balancing. Kendo can run on today's commodity hardware while incurring only a modest performance cost. Experimental results on the SPLASH-2 applications yield a geometric mean overhead of only 16% when running on 4 processors. This low overhead makes it possible to benefit from Kendo even after an application is deployed. Programmers can start using Kendo today to program parallel applications that are easier to develop, debug, and test.

Kendo

Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded applications, causes significant challenges for parallel programmers by hindering their ability to create parallel applications with repeatable results. As a consequence, parallel applications are significantly harder to debug, test, and maintain than sequential programs. This paper introduces Kendo: a new software-only system that provides deterministic multithreading of parallel applications. Kendo enforces a deterministic interleaving of lock acquisitions and specially declared non-protected reads through a novel dynamically load-balanced deterministic scheduling algorithm. The algorithm tracks the progress of each thread using performance counters to construct a deterministic logical time that is used to compute an interleaving of shared data accesses that is both deterministic and provides good load balancing. Kendo can run on today's commodity hardware while incurring only a modest performance cost. Experimental results on the SPLASH-2 applications yield a geometric mean overhead of only 16% when running on 4 processors. This low overhead makes it possible to benefit from Kendo even after an application is deployed. Programmers can start using Kendo today to program parallel applications that are easier to develop, debug, and test.

Design and Evaluation of Hybrid Fault-Detection Systems

As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have primarily considered hardware-only and software-only fault-detection mechanisms to identify and mitigate the deleterious effects of transient faults. These two fault-detection systems, however, are extremes in the design space, representing sharp trade-offs between hardware cost, reliability, and performance. In this paper, we identify hybrid hardware/software fault-detection mechanisms as promising alternatives to hardware-only and software-only systems. These hybrid systems offer designers more options to fit their reliability needs within their hardware and performance budgets. We propose and evaluate CRAFT, a suite of three such hybrid techniques, to illustrate the potential of the hybrid approach. For fair, quantitative comparisons among hardware, software, and hybrid systems, we introduce a new metric, Mean Work To Failure, which is able to compare systems for which machine instructions do not represent a constant unit of work. Additionally, we present a new simulation framework which rapidly assesses reliability and does not depend on manual identification of failure modes. Our evaluation illustrates that CRAFT, and hybrid techniques in general, offer attractive options in the fault-detection design space.

Audio-Pro with Multiple DSPs and Dynamic Load Distribution

The latest professional Karaoke system released in Japan has no ASIC for sound synthesis and effects processing, but instead a small group of load-sharing DSPs that co-operatively handle the varied and dynamically varying tasks of complex high-quality audio performance. The software-only system is a first for the audio industry, heralding a new generation of downloadable and task-sensitive software that delivers time-critical performance from distributed general-purpose silicon. The tasks of emulating a 64-voice orchestra plus real-time MPEG decode, live voice tracking with pitch and tempo following, and a full range of audio effects processing are represented in a network of active objects which are just-in-time serviced by a co-operating array of SIMD DSPs.

Reliability Optimization Models for Embedded Systems With Multiple Applications

Summary and Conclusions-This paper presents four models for optimizing the reliability of embedded systems considering both software and hardware reliability under cost constraints, and one model to optimize system cost under multiple reliability constraints. Previously, most optimization models have been developed for hardware-only or software-only systems by assuming the hardware, if any, has perfect reliability. In addition, they assume that failures for each hardware or software unit are statistically independent. In other words, none of the existing optimization models were developed for embedded systems (hardware and software) with failure dependencies. For our work, each of our models is suitable for a distinct set of conditions or situations. The first four models maximize reliability while meeting cost constraints, and the fifth model minimizes system cost under multiple reliability constraints. This is the first time that optimization of these kinds of models has been performed on this type of system. We demonstrate and validate our models for an embedded system with multiple applications sharing multiple resources. We use a Simulated Annealing optimization algorithm to demonstrate our system reliability optimization techniques for distributed systems, because of its flexibility for various problem types with various constraints. It is efficient, and provides satisfactory optimization results while meeting difficult-to-satisfy constraints.

A system-level communication synthesis approach for hardware/software systems

This paper presents a new method for modelling and synthesising a wide range complex communication schemes. These schemes can range from simple protocols that govern access to shared resources to complex protocols that are commonly used in software-only systems such as computer networks. The proposed communication synthesis method deals with both protocol and interface synthesis and is based on communication unit allocation. We highlight within this paper the usefulness of this method when synthesising communication schemes for mixed hardware/software systems.