Software Implementation Techniques Research Articles

Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium

Bitslicing is a software implementation technique that treats an N -bit processor datapath as N parallel single-bit datapaths. Bitslicing is particularly useful to implement data-parallel algorithms, algorithms that apply the same operation sequence to every element of a vector. Indeed, a bit-wise processor instruction applies the same logical operation to every single-bit slice. A second benefit of bitsliced execution is that the natural spatial redundancy of bitsliced software can support countermeasures against fault attacks. A k -redundant program on an N -bit processor then runs as N/k parallel redundant slices. In this contribution, we combine these two benefits of bitslicing to implement a fault countermeasure for the number-theoretic transform (NTT) . The NTT efficiently implements a polynomial multiplication. The internal symmetry of the NTT algorithm lends itself to a data-parallel implementation, and hence it is a good candidate for the redundantly bitsliced implementation. We implement a redundantly bitsliced NTT on an advanced 667MHz ARM Cortex-A9 processor, and study the fault coverage for the protected NTT under optimized electromagnetic fault injection (EMFI) . Our work brings two major contributions. First, we show for the first time how to develop a redundantly bitsliced version of the NTT. We integrate the protected NTT into a full Dilithium signature sequence. Second, we demonstrate an EMFI analysis on a prototype implementation of the Dilithium signature sequence on ARM Cortex-M9. We perform a detailed EM fault-injection parameter search to optimize the location, intensity and timing of injected EM pulses. We demonstrate that, under optimized fault injection parameters, about 10% of the injected faults become potentially exploitable. However, the redundantly bitsliced NTT design is able to catch the majority of these potentially exploitable faults, even when the remainder of the Dilithium algorithm as well as the control flow is left unprotected. To our knowledge, this is the first demonstration of a bitslice-redundant design of the NTT that offers distributed fault detection throughout the execution of the algorithm.

Technological assurance of the accuracy of cycloidal helical surfaces when processing them with a non-profiled tool on CNC machines

Modern designs of volumetric machines have parts containing complex-profile cycloidal screw surfaces as working bodies. The shaping of some types of this surfaces, such as the rotor surface of a conical singlescrew compressor, is possible only through the use of non-profiled tools and using specialized machining strategies. In view of the high prospects of using such structures in astronautics, robotics, medicine in the mining industry and metallurgy, there is an urgent problem of cycloidal helical surfaces accuracy during their processing on CNC machines. This work is devoted to the study of this problem. In the course of the study, a technological approach was chosen that provides control of the shape accuracy parameters when processing these surfaces, which consists in programmed feed control during processing. An analytical formalized algorithm for calculating the amount of feed change was integrated into an automated system for calculating the tool path, which made it possible to carry out experimental processing of a series of samples. The results of a metrological study of the accuracy of the shape of samples processed using a software-implemented technique for increasing the accuracy of the cross-section of cycloidal helical surfaces are presented. The efficiency of application of the proposed technique in the processing of miniature cycloidal helical surfaces is shown. Therefore, for the singlescrew micro-dispenser selected as a characteristic part of the rotor, it was possible to reduce the deviation from the circularity of the crosssectional profile of the cycloidal screw surface by more than three times. This demonstrates the possibility of increasing the accuracy of processing a complex-shaped surface by modifying the code of the control program without using additional equipment or more advance tools.

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

This article proposes a software error mitigation approach that uses the single instruction multiple data (SIMD) coprocessor to accelerate computation over redundant data. In addition, an external IP connected to the microprocessor’s trace interface is used to detect errors that are difficult to cover with software-implemented techniques. The proposed approach has been implemented in an ARM microprocessor, and an irradiation campaign with neutrons has been carried out at Los Alamos National Laboratory. Experimental results demonstrate the high error coverage (more than 99.9%) of the proposed approach. The neutron cross section of errors that were not corrected nor detected was reduced by more than three orders of magnitude.

Opportunities for software reuse in an uncertain world: From past to emerging trends

AbstractMuch has been investigated about software reuse since the software crisis. The development of software reuse methods, implementation techniques, and cost models has resulted in a significant amount of research over years. Nevertheless, the increasing adoption of reuse techniques, many of them subsumed under higher level software engineering processes, and advanced programming techniques that ease the way to reuse software assets, have hidden somehow in the recent years new research trends on the practice of reuse and caused the disappearance of several reuse conferences. Also, new forms of reuse like open data and feature models have brought new opportunities for reuse beyond the traditional software components. From past to present, we summarize in this research the recent history of software reuse, and we report new research areas and forms of reuse according to current needs in industry and application domains, as well as promising research trends for the upcoming years.

Selective Fault Tolerance for Register Files of Graphics Processing Units

The high computing efficiency of graphics processing units (GPUs) makes them attractive for both high-performance computing and safety-critical applications, such as the automotive and aerospace ones. For both application domains, reliability is a major concern. This paper aims at providing guidelines to improve the reliability of GPUs register file without jeopardizing the device’s computing efficiency. We advance the knowledge of GPUs’ reliability by investigating register file criticality, which is the probability for a fault in a register to propagate and affect computation. Then, we propose and validate selective fault-tolerance techniques for GPUs register file that can be applied at hardware or software level. Results show that both implementations are well suited to detect faults affecting computation. However, although hardware-implemented techniques are able to detect faults that are triggering a crash, software-implemented techniques may not be sufficient to guarantee sufficient coverage for crashes.

Defects localization research in photovoltaic cells: Methods and devices

The article presents a method to determine local defects in solar photovoltaic cells (PVC). It is based on the non-contact measurement of PVC area temperature distribution by a special thermovision system when applying forward and reverse voltage to the cell. Distribution of PVC surface temperature is determined by nonuniformity of current density (because of local defects) and reveals itself in the intensity of thermal radiation in the infrared spectrum (IR). The difference between the light detector signals when applying a forward or reverse voltage to PV cells and in the absence of applied voltage to the PVC is used to eliminate the effect of IR light patch, surface irregularities emissivity of solar cells, heterogeneity sensitivity light detector array. The hardware and software implementation techniques using the focal plane array of infrared 3–5 micron spectral range and 320 × 256 elements size are presented.

A study of energy-aware implementation techniques: Redistribution of computational jobs in mobile apps

As devices like smartphones and tablets have been adopted by millions of users, the offer of mobile software products and services has as well evolved significantly. Current mobile software products require hardware resources, computer job and network connectivity that is reflected in increasing power needs. This power demand represents a major challenge to the strong autonomy requirement of mobile devices, powered by batteries. As a consequence, one of the most important qualities of mobile software development is the ability to produce applications that consume energy resources wisely. To accomplish this goal, different approaches have been proposed, including energy-aware software design and implementation techniques. The energy aware software design techniques considered in this work are two: Method Reallocation, which refers to the placement of pieces of code in different execution scopes within a single target (e.g., kernel space, application space, shared library space), and Method Offloading, which refers to the placement of pieces of code in external resources in different scopes (for instance a remote server). Both techniques aim to economize resources like processing power, and memory usage, but always upon the expenses carried by interfacing, communication and network overhead. Our goal is to investigate how each one can contribute to reduce the overall energy consumption of a mobile software application. As an experiment, we utilized a mobile application that runs software benchmarks coded in Java and C. We exercised the benchmarks in different execution scopes within the handheld target and a remote server counterpart, measuring the amount of energy required to complete each job. After determining the energy consumed by each routine for each execution scope, we identified in what cases it is convenient to reallocate the processing job, and when it is advisable to offload it to an external execution environment.

SOFTWARE IMPLEMENTED HARDWARE-TRANSIENT FAULTS DETECTION

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.

소프트웨어 글로벌화를 위한 제품 라인 아키텍처 설계 기술

Abstract Software globalization is the supporting process of adapting computer software to different country and culture. Most efforts for software globalization have been focused on the development of software implementation techniques or tools. However, global software sold worldwide has different requirements implied by different contexts, and the difference of requirements may derive different architectural design. In this paper, we define such architectural design knowledge as knowledge models and propose a method for developing and using the knowledge models for software globalization. Also we use set-top box middleware systems for digital data broadcast to validate the applicability of the proposed models and methods. Key Words : Software globalization, product line architecture, design knowledge model, architectural design method, digital data broadcast. * 정회원, 한성대학교 정보시스템공학과접수일자: 2013년 2월 15일, 수정완료 2013년 3월 15일 게재확정일자: 2013년 4월 12일 Received: 15 Feburary 2013/ Revised: 15 March 2013 /Accepted: 12 April 2013

An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures

In this paper, a software behavior-based technique is presented to detect control-flow errors in multi-core architectures. The analysis of two key points leads to introduce the proposed technique: (i) employing under-utilized CPU resources in multi-core processors to check the execution flow of the programs in parallel with their executions to moderate the performance overhead of previous software-based techniques, and to enhance the applicability of them in current architectures. (ii) Adjusting the locations of additional statements in a given program in order to increase the ability of detecting possible control-flow errors along with significant reduction in overheads. To evaluate the proposed technique, a quad-core processor system is used as the simulation environment, and the behavior of several well-known single- and multi-threaded benchmarks have been studied. The experimental results, regarding to both detection coverage and performance overhead, demonstrate that on average about 93% of the control-flow errors can be detected by the proposed technique with just about 10% performance overhead, compared to at least 30% imposed by the previous techniques.

The ConstructibleSetTools and ParametricSystemTools modules of the RegularChains library in Maple

We present two new modules of the RegularChains library in Maple: ConstructibleSetTools which is the first distributed package dedicated to the maniputation of (parametric or not) constructible sets and ParametricSystemTools which is the first implementation of comprehensive triangular decomposition. We illustrate the functionalities of these new modules by examples and describe our software design and implementation techniques. Since several existing packages have functionalities related to those of our new modules, we include an overview of the algorithms and software for manipulating constructible sets and solving parametric systems.

Detecting computer-induced errors in remote-sensing JPEG compression algorithms

The JPEG image compression standard is very sensitive to errors. Even though it contains error resilience features, it cannot easily cope with induced errors from computer soft faults prevalent in remote-sensing applications. Hence, new fault tolerance detection methods are developed to sense the soft errors in major parts of the system while also protecting data across the boundaries where data flow from one subsystem to the other. The design goal is to guarantee no compressed or decompressed data contain computer-induced errors without detection. Detection methods are expressed at the algorithm level so that a wide range of hardware and software implementation techniques can be covered by the fault tolerance procedures while still maintaining the JPEG output format. The major subsystems to be addressed are the discrete cosine transform, quantizer, entropy coding, and packet assembly. Each error detection method is determined by the data representations within the subsystem or across the boundaries. They vary from real number parities in the DCT to bit-level residue codes in the quantizer, cyclic redundancy check parities for entropy coding, and packet assembly. The simulation results verify detection performances even across boundaries while also examining roundoff noise effects in detecting computer-induced errors in processing steps.

Best Practice (BPM)

Just as BPM (business process management) technology is markedly different from conventional approaches to application support, the methodology of BPM development is markedly different from traditional software implementation techniques. With CPI (continuous process improvement) as the core discipline of BPM, the models that drive work through the company evolve constantly. Indeed, recent studies suggest that companies fine-tune their BPM-based applications at least once a quarter (and sometimes as often as eight times per year). The point is that there is no such thing as a "finished" process; it takes multiple iterations to produce highly effective solutions. Every working BPM-based process is just a starting point for the future. Moreover, with multiple processes that could benefit from BPM-style automated support, the issue becomes how to support dozens or even hundreds of engagements per year.

A low-cost testing for transient faults

Unconventional and low - cost software implemented testing technique for processor transient faults are briefly discussed here. On-line signatures of the Processor Status Register have been used here for detecting transient faults.

Comparison of physical and software-implemented fault injection techniques

This paper addresses the issue of characterizing the respective impact of fault injection techniques. Three physical techniques and one software-implemented technique that have been used to assess the fault tolerance features of the MARS fault-tolerant distributed real-time system are compared and analyzed. After a short summary of the fault tolerance features of the MARS architecture and especially of the error detection mechanisms that were used to compare the erroneous behaviors induced by the fault injection techniques considered, we describe the common distributed testbed and test scenario implemented to perform a coherent set of fault injection campaigns. The main features of the four fault injection techniques considered are then briefly described and the results obtained are finally presented and discussed. Emphasis is put on the analysis of the specific impact and merit of each injection technique.

A Software Implementation Technique for Simulation of Ethernet Local Area Networks

A software system designed for simulating Ethernet, Fast Ethernet, and Gigabit Ethernet local area networks (LAN) is described. Implementation-specific features of programs simulating the operation of switch-based full-duplex and half-duplex networks are considered. A subsystem for simulating the stochastic behavior of programs based on full-duplex LAN protocols is described.

Constructing dependable Web services

The majority of today's millions of Web sites offer read-only access to relatively small amounts of infrequently changing information. The load on these sites is usually small, and services can often be hosted as background tasks on general-purpose workstations. Concern for the quality of service (QoS) presented to users at these sites is generally not primary. Conversely, a much smaller number of sites are very popular; they support heavy loads and must meet user expectations regarding QoS to maintain their popularity. We discuss issues involved in supporting high-volume, high-reliability Web services. We begin by surveying the diverse technical challenges and constraints posed in this environment, followed by currently used hardware and network based approaches to meeting the scalability requirements and software-implemented techniques to addressing fault tolerance. However, these approaches do not scale well, so we discuss possible alternatives.

Object-oriented state machines

Software specification and implementation techniques based on state machines simplify design, coding, and validation. However, large systems require complex state machines. Incremental construction techniques can control this complexity. In this paper, we present a construction technique that permits derivation of complex state machines from simpler state machines. The technique uses subclassing, composition, delegation, and genericity to incrementally modify and combine simpler machines.In addition, we present a novel implementation technique that uses exactly one table-lookup and one addition to dispatch events on derived state machines, no matter the depth of the derivation. As an example, we describe the derivation of a complicated distributed virtual memory scheme from a simple paging virtual memory scheme.

Efficient implementation of binary morphological image processing

Morphological image processing is an important tool for a broad range of problems in image processing. A 512-entry table lookup method is used for real-time implementation. But it is not efficient to transfer this method directly into software. The author proposes a fast software implementation technique, in which a 256-entry lookup table containing neighborhood information is built and a dynamic table lookup process is applied to reduce the number of logical matching operations and the number of accesses of the neighboring pixels. In this proposed method only the foreground pixels, which are pixels on the object, are processed. Among the foreground pixels, only at the starting pixel of each "run" of l's is it necessary to read the eight neighboring pixels. For the other pixels, it is necessary to read only three neighbors. This method shows a significant improvement in timesaving. In addition, for systems supporting fast access to consecutive address memory, the author proposes another implementation, which treats the image as a contiguous block of memory. Thus advantage is taken of RAM technology.

The AT&TKorbx® System

This paper describes the AT&T KORBX system, which implements certain variants of the Karmarkar algorithm on a computer that has multiple processors, each capable of performing vector arithmetic. We provide an overview of the KORBX system that covers its optimization algorithms, the hardware architecture, and software implementation techniques. Performance is characterized for a variety of applications found in industry, government, and academia.