Processor For Software Defined Radio Research Articles

Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current wireless communication protocols can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50 Mbps. Some of the fastest software implementations of the advanced encryption standard (AES) only achieve 20 Mbps on our reference platform. In order to have secure software-defined radio, the security processing gap must be addressed. This paper presents instruction set architecture (ISA) extensions for the sandblaster digital signal processor (DSP). The sandblaster DSP is a multithreaded processor for SDR that issues multiple operations each cycle and supports vector operations. Our proposed ISA extensions and hardware designs provide significant performance improvements for AES cryptography and should also work well with other types of embedded processors.

Programmable processor implementations of [formula omitted]-best list sphere detector for MIMO receiver

An increasing number of standards in wireless communications have encouraged to study programmable processors as platforms for flexible receivers. A multiple-input multiple-output (MIMO) antenna system combined with orthogonal frequency division multiplexing (OFDM) technique has been introduced in many wireless communications standards, such as in the third generation long term evolution (3G LTE). The MIMO-OFDM system requires an efficient detector and a platform support for parallel processing of multiple subcarriers. A K -best list sphere detector (LSD) provides for near optimal decoding performance and a fixed throughput making it an interesting algorithm from the point of view of practical implementations. In this paper, we compare the implementations of the K -best LSD on four processor platforms: a digital signal processor (DSP), software defined radio (SDR), application-specific processor (ASP) and application-specific instruction-set processor (ASIP). The DSP is a popular very long instruction word (VLIW) device (TMS320C6455), the SDR processor employs multithreading and multiple cores (SB3500 core processor), the ASP is based on transport triggered architecture (TTA), while the ASIP is the SDR processor enhanced with a special instruction-set extension for sorting. A 2 × 2 MIMO antenna system with 64-quadrature amplitude modulation (64-QAM) is assumed. The chosen list sizes K = 8 and 16 are based on simulation results carried out in MATLAB environment with the third generation long term evolution (3G LTE) parameters. The proposed ASIP achieved a promising throughput of 32.0 Mbps, where the software defined radio (SDR) implementation on the SB3500 core processor suffers from an inefficient software sorter. The ASP, in which the minimized hardware complexity has been the goal, achieves a throughput of 7.6 Mbps. However, more essential examination is related to the symbol time, which sets strict parallel processing requirements to the programmable processors.

Energy-performance Exploration of a CGA-based SDR Processor

Software-Defined Radio (SDR) provides the flexibility to enable cost-effective multi-mode terminals. However, the growing complexity of the new communication standards, which need to be executed with the reduced energy budget required by battery-powered devices, is still challenging architects. Although Coarse Grain Array (CGA) -based processors extended with domain specific instructions are considered strong candidates to undertake both the high-performance and low power, the lack of efficient methodologies to derive optimal instances of such an architecture paradigm is still a major limitation. In this paper, an extensive energy-performance exploration of a CGA-based SDR processor is presented. This approach targets sufficient relative accuracy on the optimization metrics, which assures meaningful comparisons between different instances, while the absolute accuracy is relaxed and traded off against simulation time. The balance between the different sources of architectural parallelism, such as data and instruction level parallelism is crucial in order to achieve the required performance at minimum energy cost. Accordingly, the proposed method is used to select the optimal DLP---ILP combination required to run the symbol-based baseband processing of a 100 Mbps+ WLAN (Wireless Local Area Network) receiver in a CGA-based processor. As a result, a 4 × 4 array with four ways SIMD (Single Instruction, Multiple Data) extensions is shown to be the optimal instance, providing minimum energy consumption and real-time processing guarantees.

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor's architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor's programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.