Software Defined Radio Channelizers Research Articles

A conducted emission mitigation method for software-defined radios through vector signal cancellation

Recently, Software-Defined Radio (SDR) has gained great popularity owing to its attractive merits, such as flexible signals configuration in multiple channels. However, commercial SDR equipment also has large spurious emissions in the Transmitting (Tx) channel. This paper presents a cascaded model for the Conducted Emission (CE) properties of a general SDR platform, which captures all the key components with high precision. Based on a deeper understanding of the CE properties, a mitigation method is proposed for suppressing the spurious emissions of an SDR Tx channel. This method is based on an efficient vector signal cancellation scheme, in which multiple SDR channels are adopted to suppress the second- and third-order harmonic signals simultaneously. A hardware prototype with dual SDR channels is built and measured for verification. Experimental results show that the suppression level of the third-order harmonic signal is 24 dB on average in the frequency range of 100 MHz to 3000 MHz. The theoretic limit of the suppression level is related to the magnitude and phase errors, and the suppression level may be further improved by calibrating each SDR channel.

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

PurposeDigital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.Design/methodology/approachThe distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.FindingsThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.Originality/valueThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Low complexity reconfigurable modified FRM architecture with full spectral utilization for efficient channelizers

This paper proposes a design of low complexity, reconfigurable, and narrow transition band (NTB) filter bank (FB). In our proposed Modified Frequency Response Masking (ModFRM) architecture, the modal filter and complementary filter in the conventional FRM approach are replaced by a power complementary and linear phase FB. Additionally, a new masking strategy is proposed by which an M-channel FB can be designed by alternately masking even channels and odd channels. By using this masking strategy, it is only necessary to modulate the masking filters over the multiple spectra replicas appearing in [0,2π] to generate uniform ModFRM FB. Also, the reconfigurability of filter banks can be achieved by adjusting the interpolation values appropriately, to obtain more masking responses. The results indicate that the proposed method requires substantially fewer multipliers in comparison to the reconfigurable FB existing in the literature. Finally, nonuniform FB is generated from the uniform FB by combining nearby channels and are used for the extraction of different communication standards in the software defined radio (SDR) channelizer. When more channels are to be extracted, the proposed scheme can achieve a reduced hardware complexity in comparison to other filter bank based SDR channelizers.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

PurposeIn this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.Design/methodology/approachThe modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.FindingsBoth RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.Originality/valueThe DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Analysis of Different Rational Decimated Filter Banks Derived From the Same Set of Prototype Filters

This paper proposes the design and analysis of different rational decimated non-uniform filter banks (RDNUFBs), in which channels with different rational sampling factors are derived by merging the channels of an initial RDNUFB. The feasibility of the merged RDNUFB is analyzed in terms of frequency selectivity, aliasing cancellation, phase distortion, and amplitude distortion. The necessary conditions for the resultant filter bank to be alias free and to possess the linear phase property, are derived. The proposed reconfigurable RDNUFB is deployed to extract various communication standards in the software defined radio (SDR) channelizer, and is found to reduce the hardware complexity when compared to other filter bank based SDR channelizers, when a large number of channels are extracted.

Selection and Application of the Data Transfer Operating Protocol Software Architecture for the Software-Defined Radio

Introduction. The demodulator structure is described and decoding algorithm for signal-code constructions development is presented. The structure and functional description of the developed software (SW), which is designed for the installation of the software-defined radio in the radio stations layout, are presented. The frame structures of the broadcast and half-duplex protocols, modulation/demodulation and subsequent digital signal processing in existing and prospect radio communication systems are considered.Objective. Investigation of modulation/demodulation methods and subsequent digital signal processing along with requirements imposed by them on the network stations equipment and system operation algorithms.Materials and methods. The software for the software-defined radio system layout is developed to demonstrate the reliability and operability of the proposed algorithm and transmission protocol. It can be used to receive and transmit information by using ionospheric reflections. Present design takes into account existing standards and amateur systems such as WinLink and information systems (digital and analog) for the "physical" and "channel" levels.Results. The structure and functional description of the developed software for the software-defined radio system layout are given. The possible realization of the software-defined radio channel for data receiving and transfer by using ionospheric reflections is presented. The results of technical solutions experimental testing are shown. The software can use hardware and software to control the transceiver module, which includes the SunSDR2 transceiver and antenna amplifier.Conclusion. The structure and functional description of the developed software are presented as a result of the software architecture selection and its application investigation. It is concluded that the reliability and operability justification of the proposed algorithm and transmission protocol is relevant in a field of the digital receivers development for communication systems of various purposes. The presented experimental studies data on verification of the proposed algorithm show the feasibility of present solutions on the qualitative utilization of the channel resource by using the described code structure. The present results allow to determine the most appropriate and efficient way of the software development allowing to create a technique that can meet the maximum number of possible assignments of radio access channels.

Low complexity reconfigurable channelizers using non-uniform filter banks

A Software Defined Radio (SDR) channelizer needs reconfigurable sharp filter banks with low implementation complexity. In this paper, the design of non-uniform Modified Discrete Fourier Transform filter bank (MDFT FB) is proposed to be used in SDR channelizer. The frequency response masking technique is used to design the prototype filter which gives sharp filters with lower hardware complexity, compared to the finite impulse response filters. The canonic signed digit (CSD) representation is used in the design, to convert the continuous filter coefficients into discrete coefficients. Multi-objective artificial bee colony algorithm is utilized to improve the performance degradation when the CSD represented filter coefficients are used. Further, the shift inclusive differential technique with common sub-expression elimination is used to reduce the number of adders. Xilinx ISE is used to verify the hardware requirement, for the implementation of the non-uniform MDFT FB. Hence low complexity reconfigurable SDR channelizers using non-uniform MDFT FB is proposed in this paper.

Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer

A software-defined radio (SDR) channelizer extracts narrowband channels from the wideband signal. The impulse response of this filter is required to change with the desired channel to be extracted from the wideband input. A reconfigurable filter is used instead of fixed filters to implement the channelizer in a resource-constrained environment. In this paper, we present a throughput-scalable reconfigurable architecture for SDR channelizer. The proposed structure processes a block of L input samples and produces one block of L outputs in every clock cycle. The register complexity of the proposed structure is independent of throughput, whereas multiplier and adder complexity increases proportionately. A significant number of registers are saved when the proposed structure is implemented for larger filter-length and higher block-sizes. Theoretical estimates show that the proposed structure for the block-size 8 and filter-length 32 involves 256 extra multipliers and 105 extra adders against 6912 MUXes, 8 less registers than those of the existing similar structure, and it offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure of block-size 8 and filter-length 32 involves 41 % less area-delay product and 22 % less energy per sample than those of the existing structure and offers nearly 6 times higher sampling rate than the other. At the normalized sampling rate, the proposed structure for filter-length 16 consumes 18 % and 22 % less power than the existing structure for block-sizes 4 and 8, respectively.

Reconfigurable channel filtering and digital down conversion in optimal CSD space for software defined radio

Software defined radio (SDR) is a platform for using the same hardware to support multiple wireless communication standards. The channelizer in the SDR is used to separate the channels from the wideband signal. The features required for using the same hardware to switch between different standards are reconfigurability and low complexity. To achieve this, we use a variable bandwidth filter (VBF) with facility for the reduction and enhancement of the bandwidth, without changing the filter coefficients. This paper proposes an optimal and multiplier-less implementation of a baseband channel filter for supporting the bandwidth requirements of various wireless communication standards. This paper also discusses the concept for using it as a multi-band SDR channelizer for the direct conversion of signals from a wideband input to the baseband signal without using an intermediate stage. Frequency response masking (FRM) filter with continuous coefficients is designed and modified harmony search algorithm is used for finding the optimal canonic signed digit representation for the multiplier-less implementation. This reduces the complexity and power consumption. The VBF with the optimized FRM filter is evaluated for the selectable bandwidths starting from 1.25 to 8MHz, which covers the bandwidth requirements of a wide range of wireless communication standards.

Reconfigurable Low Area Complexity Filter Bank Architecture Based on Frequency Response Masking for Nonuniform Channelization in Software Radio Receivers

The most computationally demanding block in the digital front-end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Channelizers are employed in the SDR receivers for extracting individual channels (frequency bands) from the digitized wideband input signal. Reconfigurability and low complexity are the two key requirements in an SDR channelizer. A new reconfigurable filter bank (FB) architecture based on frequency response masking (FRM) for SDR channelizers is proposed. The proposed FB offers reconfigurability at the architectural level and at the channel filter level and is capable of extracting channels of nonuniform bandwidths corresponding to multiple wireless communication standards from the digitized wideband input signal. Design examples show that the proposed FB offers multiplier complexity reduction of 84% over the conventional per-channel (PC) approach, which is best suitable for the extraction of channels of nonuniform bandwidth. The proposed FB has been synthesized on 0.18 μm complementary metal oxide semiconductor (CMOS) technology and compared with the PC approach. Synthesis results show that the proposed FB offers area reduction of 85%, power reduction of 48.5%, and improvement in speed of 56.7% over the PC approach. The proposed FB has been implemented on Xilinx Virtex 2v3000ff1152-4 FPGA and tested using real-time inputs from a vector signal generator.

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.

Design of Software-Defined Radio Channel Simulator for Wireless Communications: Case Study With DSRC and UWB Channels

The software-defined radio (SDR) channel simulator is designed for testing the baseband transceiver of various wireless communication systems. The SDR architecture and the reconfiguration scheme used for changing the channel conditions and reconfiguring the hardware of the processing modules in the SDR channel simulator are presented. The simulator is capable of simulating four multipath fading channels and dedicated fading channels operating in various air interface specifications of wireless communication systems according to the demands of users. An example of the SDR channel simulator implemented with the air interface standards of dedicated short-range communications (DSRC) and ultrawideband (UWB) systems is carried out to observe the characteristics of two multipath fading channels and the hardware reconfiguration capability of processing modules and validate its correctness. The functions of the proposed SDR channel simulator can be extended to other new or modified air interface specifications of wireless communication systems without any hardware modification.

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.