Software Defined Radio Applications Research Articles

An FPGA-Based Reconfigurable FIR Filter for SDR Applications

This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.

Application of Software-defined radio in communication systems

The paper presents examples of solving urgent telecommunication tasks using the technology of Software-defined radio systems (SDR). The problem and the role of SDR in its solution are described for each example. The comparison of the main characteristics and structure of the hardware components of the SDR, which are used in the considered examples, is given. The results of the work with the debugging module for the Russian microchip 1288HK1T according to the scenario of the demo version of functioning are presented.

A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , enabling radio applications in which latency is a principal constraint.

A 0.1–9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology

This article describes a design for a frequency synthesizer architecture based on a phase-locked loop (PLL) for avionic software-defined radio (SDR) applications at up to 9 GHz. Three basic architectural schemes: wide range voltage-controlled oscillator (VCO), single sideband (SSB) mixing, and multiple VCOs can be used to extend the frequency ranges. This article compares these schemes through quantitative evaluation to select the best synthesizer architecture to use according to the application specs. The chosen scheme is an optimized combination of a single VCO and a single SSB mixer. Using a quadrature VCO (QVCO) with a switched capacitor (SC) bank, the synthesizer provides a wide frequency band of operation ranging from 100 MHz to 9 GHz covering several avionic communication applications and several existing wireless standards’ frequency requirements. The proposed QVCO is able to generate in-phase and quadrature-phase signals spread into a frequency band between 6 and 9 GHz providing a tuning range of 40% at a center frequency of 7.5 GHz. The QVCO exhibits a phase noise of −107 dBc/Hz, at a 1-MHz offset frequency, while generating a 8-GHz carrier frequency. Its power consumption is of 3.4 mW. With a loop bandwidth of 120 kHz, the frequency synthesizer generates a phase noise, measured at 8 GHz, of −106.4 dBc/Hz at a 1-MHz frequency offset. The overall power consumption of the synthesizer to generate a 140-MHz carrier frequency is 26.57 mW from a 1.2-V supply. The frequency synthesizer is implemented in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.72 \times 0.72$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

PurposeDigital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.Design/methodology/approachThe distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.FindingsThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.Originality/valueThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Stratospheric balloon tracking system design through Software Defined Radio applications: STRAINS experiment

The new concept aerospace mission profiles, such as stratospheric airships or suborbital vehicles, impose new requirements for the tracking and surveillance systems, with particular regards to manned missions. New technologies and innovative tracking systems can be supporting such operations. The STRAINS (Stratospheric Tracking Innovative Systems) Experiment, conceived by Sapienza University of Rome and ALTEC (Aerospace Logistics Technology Engineering Company) and supported by ASI (Italian Space Agency), to be launched in Q3/Q4 2021, is aiming at demonstrating TDOA (Time Difference of Arrival), FDOA (Frequency Difference of Arrival) and single station tracking for a Zero-Pressure Balloon Flight in the framework of the HEMERA H2020 balloon launch infrastructure. This paper describes the design of the STRAINS stratospheric experiment, including the stratospheric and the ground segment, the analyses carried out for optimizing the experiment functionalities, the mission analysis for defining the multi-lateration stations locations and the performance evaluation for the designed TDOA tracking system.

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

PurposeIn this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.Design/methodology/approachThe modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.FindingsBoth RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.Originality/valueThe DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios.

A reconfigurable -boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked -boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.

Undergraduate Curriculum to Teach and Provide Research Skills on Hardware Design for SDR Applications in FPGA Technology

Software Defined Radio (SDR) technologies play today an important role in modern wireless networks due to their flexibility to implement re-configurable hardware designs. In light of the importance to operate and develop such technologies, academic programs in the communications engineering field demand an introduction to Digital Signal Processing (DSP) and SDR communication schemes accordingly. Typically, the teaching of this subject is afforded through projects and hands-on activities in classrooms. However, provided their relevance in the current state-of-the-art, this topic also provides a framework to teach soft skills concerning research abilities in students. This paper introduces an academic program to the development of SDR functionality as well as research skills based on exposure to state-of-the-art research. Through projects, hands-on activities are conducted to teach digital signal processing designs using Field Programmable Gate Array (FPGA) technology. The course aims to develop technical skills to implement communication system blocks. Besides, workshops and seminars are prepared to support the development of research and communication skills. The proposed course is flexible to incorporate on a given academic program as an elective subject to further support topics related to communication theory and discrete-time signals. Learning outcomes are designed to develop enhanced technical skills in SDR design and simultaneously a critical discussion of the devised solutions in light of the state-of-the-art. Also, skills related to identifying, formulating, and discussing engineering problems are further reinforced. Results from supported projects developed in the classroom exhibit completed assignments superior to 90% of participant students. Learning objectives concerning the technical skills were successfully covered (90%) in comparison to research and communicating skills (80%). Additionally, research skills and the ability to disseminate knowledge gradually improved in seminars. Finally, results of the current course exhibit improvements of 25% regarding the acquired skills in digital signal processing in comparison to previous courses.

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications

This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.

Bacterial Foraging Optimization of Speech Coder for Software Defined Radio Application

The paper presents integration of Discrete Wavelet Cosine Transform technique and Bacterial Foraging Algorithm (BFO) for the development and optimization of speech coder. It is depicted how by filtering the limited number of high energy components of transformed coefficients with parallel programming can maintain the speech signal quality in coding over wide range of bit rates. The performance of existing and proposed speech coding techniqueattributes such as compression ratio, coding delay, computational complexity and quality of reconstructed speech is examined for multiple bit rates and compared with other existing speech coding techniques in Matlab environment. The result showsimprovement in performancewith respect to all attributes at the cost of increase in complexity.

Improved Real Time GPS RF Data Capturing for GNSS SDR Applications

Global Navigation Satellite System (GNSS) software-defined radio (SDR) is a programmable software receiver, primarily used to receive satellite data and provide user position. It is flexible and cost-effective compared to conventional satellite receivers. In GNSS SDR, recording the live raw data in real-time is a challenging task as large data are sent by the satellites at a very high speed. These data are further processed by the baseband algorithms which provide the user location. The accuracy of the tracked location depends on the precision of the data captured. Among the available hardware receivers, USRP RF front end kit provides flexibility. This paper proposes an efficient approach to capture the real-time GPS data by using the USRP N210 kit. If the receiver is not tuned with the exact parameters, the problems of data overflow and underflow occur. A novel data controlling queue thread method is introduced to overcome this problem. It is evident that the results obtained from our method are very close to those of Ublox GPS.

Design and Implementation of Low Power High Speed Symmetric Decoder Structure for SDR Applications

The key objective of this project is to design a decoder which can be used for hardware purposes. Hardware, here accompanies with software which is more we can discuss as a Software Defined Radio application. The decoder implemented here offers to new radio equipment (SDR), the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. Large tree decoder is made by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system a less complexity one. The structure obeys regularity and modularity concepts of VLSI circuit, thus is easy to fabricate using cell library elements. Design a Tree Decoder proposed architecture for SDR application on FPGA. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using Xilinx Vivado design suite.

A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider

A 30 MHz–3.6 GHz wideband frequency synthesizer with a self-biased oscillator and quadrature-input quadrature-output (QIQO) dividers for software-defined radio applications is presented in this brief. The self-biased oscillator employs a novel cross-coupled negative-Gm pair that performs an equivalent linearized negative resistance, mitigating the noise folding process. The QIQO dividers are utilized to divide the quadrature signals and incorporate with a quadrature single sideband mixer for post synthesizing. The synthesizer is implemented in TSMC 180-nm RF CMOS process and provides a phase noise performance of −125.4 dBc/Hz and −122.9 dBc/Hz at 1 MHz offset under 1.8- and 2.7-GHz carriers, respectively. The maximum power consumption is 135 mW and the die size, including pads and I/O is 2.9 mm $^{{2}}$ .

0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application

This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2-V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low-power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low-power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low-power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.

Development of Custom Interface Driver between USRP and SoC devices for SDR Applications

Global Navigation Satellite System (GNSS) is used to provide position based on satellite constellation. The GNSS Software defined radio (SDR) is a software approach which is more flexible than Hardware receivers. In GNSS SDR, most of the RF frontends are interfaced with a host-Personal Computer (PC). The host-PC based GNSS-SDR systems suffer from computational complexity and latency between IQ samples of GNSS signals. There are several RF front ends available to capture the real time signals. Among all these, USRP RF frontends are flexible for the prototype development. Earlier the host-PC was interfaced with the USRP device for the SDR implementation. In this work the, USRP N210 is interfaced with Zynq SoC device for GNSS SDR applications. This approach will introduce parallelism, which in turn leads to reduction in latency between IQ samples. A custom Ethernet driver to interface the USRP N210 with Zynq SoC device is proposed. The experimental results showcase that the proposed SoC based approach is suitable for GNSS-SDR prototype.

Reconfigurable Chireix Outphasing Power Amplifier Over Multiple Frequency Bands

This brief presents a new design scheme to expand the operating frequency range of outphasing power amplifier (PA) which is useful for software-defined radio applications. The proposed design scheme offers reconfigurability to multiple operating bands by using reconfigurable Chireix combiner along with wideband PA. For efficiency enhancement at output power back-off at multiple operating frequencies, Chireix combiner should provide correct reactance compensation at each operating frequency. This is achieved by utilizing tunable compensating network, which can be reconfigured to multiple operating frequencies. The proposed methodology is experimentally verified in radio frequency/digital hybrid DSP/field programmable gate array-based platform. The measurement results show efficiency enhancement upto 6–7-dB output power back-off over ±25-MHz bandwidth around 1.65, 2.1, and 2.35 GHz.

Design of parallel and pipelined DA based OBC fir filter for software defined radio

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.