Software-based Self-test Research Articles

Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT

Throughout device testing, one key parameter to be considered is the switching activity (SWA) of the circuit under test (CUT). To avoid unwanted scenarios due to excessive power consumption during test, in most cases the SWA of the CUTs must be retained to a minimal value when the test stimulus is applied. However, there are specific cases where the opposite, namely the SWA maximization within the CUT, or a certain sub-module of it, can be proven beneficial. For example, during dynamic Burn-In testing we aim at maximizing the internal stress by applying suitable stimuli. This can be done in a functional manner by following the Software-Based Self-Test paradigm. However, generating such suitable programs represents a costly and arduous task for the test engineers. We consider the case where the CUT is a pipelined processor core and we aim to maximize the SWA of certain core sub-modules. We present a comprehensive methodology based on formal methods, able to automatically generate the best two-instruction stress-inducing sequence for the targeted processor module. The generated stimulus is composed of a short, arbitrarily-long repeatable sequence of a pair of assembly instructions, thus guaranteeing the maximum possible constant switching activity. The proposed method was applied to the OpenRISC 1200 and the RI5CY (PULP) processor cores demonstrating its effectiveness when compared to other methods. We show that the time for generating the best repeatable instruction sequence is limited in most cases, while the generated sequence can always achieve a significantly higher repeatable and constant SWA than other solutions.

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip

Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques

During device testing, an important parameter to be considered by the test engineers is the switching activity (SWA) of the circuit under test (CUT). It is well known that the SWA must be kept to a minimum in order to avoid catastrophic scenarios on the CUTs, e.g., unacceptable peak power consumption or over-stressing that can lead to an artificial yield loss. However, there are scenarios, where the inverse, namely the switching activity maximization, can be proven beneficial. For example, this happens during Burn-In testing, when we aim at exercising the circuit under extreme operating conditions in terms of temperature and temperature gradients to accelerate aging phenomena in a controlled manner. In some cases, this is achieved by applying to the CUT stimuli in a functional manner, based on the Software-Based Self-Test (SBST) paradigm. Though, the generation of such appropriate programs for this task represents a challenge for the test engineers. In this paper we consider the scenario where the modules to be stressed are the units of a pipelined processor. We present a method, based on an evolutionary approach, that is able to automatically generate maximum stress programs, i.e., sequences of instructions achieving a high switching activity in the target module. With respect to other approaches, the generated sequences are built from the ground-up, are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the generated stimuli from the proposed method are effective in achieving a high value of sustained switching activity within the considered processor modules while also achieves a better results when comparing with other methods (e.g., stuck-at oriented test programs).

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.

An efficient strategy for the development of software test libraries for an automotive microcontroller family

With the introduction of the ISO26262 standard in the automotive field, numerous solutions for the in-field and on-line testing have been proposed. Among the several test solutions available, the Built-In Self-Test (BIST) approach is the most used for manufacturing test of chips, while the Software-Based Self-Test (SBST) approach is the most commonly used for on-line test the modern processors. This paper faces a very concrete problem concerning SBST development. In order to address more market demands, semiconductor industries are usually developing families of microcontroller, usually based on similar processors, instead of a single instance. This variety of architectures makes the development of SBST programs a repetitive, time and human consuming activity.The main aim of this work is to propose a methodology according with the SBST paradigm that permits to develop test programs able to achieve high coverage on different microcontrollers of the same family. The developed test programs are not showing any significant drop in coverage performance when they are used on different processors included in product of the same microcontroller family. The approach is based on the analysis of the processor hierarchy to identify the common units between the processors of the same family, first of all looking at those that show design differences. The module classification permits than to plan the most effective SBST development.A segment of industrial microcontrollers developed by STMicroelectronics for the automotive field, adapting many processors belonging to the same processor family, is used as a case of study. The experimental results demonstrate the effectiveness of the proposed approach, i.e., to reach the same fault coverage figures over many processors while dramatically reducing the development time.

On-line self-test mechanism for Dual-Core Lockstep System-on-Chips

The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system functionalities, thus in-field self-test mechanisms are mandatory. In this paper, different in-field self-test solutions are first discussed. Then, a hybrid hardware-software scheme for the on-line testing of the lockstep logic is proposed. Such a solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor. Exhaustive experiments demonstrated that it is possible to achieve a fault coverage of stuck-at faults greater than 99%, while at the same time significantly reduce the area overhead of classical approaches.

Software-Based Self-Test Techniques for Dual-Issue Embedded Processors

Nowadays, Self-Test strategies for testing embedded processors are increasingly diffused, especially for safety critical systems. Test programs can be effectively used for this purpose. This paper describes a set of systematic self-test techniques for in-order dual-issue embedded processors. The paper shows how to produce test programs suitable for the detection of faults in five classes of sub-modules: duplicated computational modules; multi-port register file; duplicated pipeline registers and feed-forward paths; pipeline interlocking logic; and pre-fetch buffer. While some techniques extend single-issue test programs, new techniques are also shown; results are illustrated for a couple of 32-bit in-order dual-issue processors included in automotive Systems-on-Chip manufactured by STMicroelectronics.

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience

The modern automobile industry is rapidly shifting toward the era of self-driving cars. Due to rapid technological development, many mechanical parts in automobiles have been switched to electronic devices. Therefore, the proportion of electronic devices in modern cars is increasing. Even though many parts have been replaced by electronic devices, vehicles still require the periodic maintenance not only for mechanical parts, but also for automotive electronics. To guarantee the high reliability of automotive Application-Specific Integrated Circuits (ASICs), automotive chips are tested during manufacturing for functional and structural defects. Moreover, automobile chips are also tested using several in-field diagnostic techniques (e.g., online Built-In Self-Test (BIST), Software-Based Self-Test (SBST)) while the chips are operating. By using these in-field diagnostic techniques, functional and structural defects in automotive ASICs, which occur in the early-life cycle and normal operation, can be detected. However, automotive semiconductor devices still require testing for aging-induced defects and soft errors to prevent critical functional failures. Moreover, aging-induced defects are hard to detect with conventional in-field diagnostic techniques which is based on BIST techniques. Thus, this work presents a secure Controller Area Network (CAN) -based Test Access Mechanism (TAM) for aging defect diagnosis with efficient soft-error resilient scan cell design for automotive ASICs. The proposed TAM incurs area overhead of 6% to 9% depending upon the selection of mode identification. Further, the proposed Aging monitoring and Soft Error Resilience Flip Flop (ARFF) incurs 22% less area and power as compared to separate implementation of the Built-In Soft Error Resilience (BISER) and the Early Capture Flip Flop (ECFF).

RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing

Software-based test (SBST) techniques are increasingly being used for testing of modern processors because of the ease of synthesis using evolutionary approaches, coverage for difficult to test faults, non-intrusive nature, low hardware overhead, etc. However, the test synthesis time required by SBST is high. In this paper, an advanced SBST technique, termed as Rapid SBST (RSBST) is proposed that reduces the overall test synthesis time by reusing the simulation responses of existing test programs of identical observability. The test codes, developed using the evolutionary process, that produce similar fault simulation results are reused for the fault evaluation. We exploit this reusability to enhance the speed of the test synthesis process. The efficacy of the proposed scheme is demonstrated on a 32-bit MIPS processor and on a minimal configuration of 7-stage SPARC V8 Leon3 soft processor. The traditional SBST synthesis requires 122 hours for the MIPS processor and 142 hours for the Leon3 processor to develop test program sets that cover 93.9% and 92.9% of the behavioral-level faults of these processors, respectively. An existing enhanced greedy-cover method, that also detects the hard-to-test faults, improves the coverage towards 96.3% for the MIPS processor and 95.8% for the Leon3 processor, but this slower test development consumes 168 hours and 172 hours, respectively. In the proposed RSBST scheme, the synthesized test codes achieve an adequate fault coverage of 96.1% for the MIPS processor and 95.5% for the Leon3 processor. This accelerated test pattern generation takes 90 hours and 98 hours for these two processors. So it may be concluded that the proposed RSBST technique speeds up the traditional SBST synthesis by a factor of 1.35 while maintaining the fault coverage above 95.5%. To validate the test quality evaluation using behavioral fault models, a strong correlation (94.8%) between the behavioral faults and gate-level faults of MIPS processor is demonstrated and verified for the proposed RSBST scheme. Also, the simulation responses of the test programs synthesized by RSBST scheme consumes only 14.25% of storage space when compared with the storage consumption of the actual simulation used by the existing test code generation methods.

New Hybrid-Based Self-Test Strategy for Faulty Modules of Complex Microcontroller Systems

In this paper, a new hybrid test strategy, called hybrid-based self-test (HYBST), is presented to test complex digital circuits such as microcontrollers. This test strategy integrates the signature multi-mode hardware-based self-test (SM-BST) with the software-based self-test (SBST). In this test strategy, the microcontroller is divided into a number of main modules, and then test subroutines are used to functionally test each module, based on its instruction set architecture (ISA). The ISA is used to generate test subroutines that represent test pattern generators (TPGs) and part of the test controller. The SMHBST represents the other part of the test controller and the test response compaction (TRC). The experimental results illustrate the superiority of the HYBST in the memory utilization, test application time, testing of internal modules of the microcontroller, and testing of general-purpose input-output (GPIO) pins of the microcontroller. In addition, an integrated test solution for fault diagnosis of the circuit boards including random logic integrated circuits (ICs) and microcontroller chips is presented to indicate a real practical test strategy.

Fault-Independent Test-Generation for Software-Based Self-Testing

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and systems-on-chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings, we propose the first fault-independent method for generating SBST procedures. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method.

HASTI: hardware‐assisted functional testing of embedded processors in idle times

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors’ results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors

Generating functional tests for processors has been a challenging problem for decades in the very large-scale integration testing field. This paper presents a method that generates software-based self-tests by leveraging bounded model checking (BMC) techniques and targeting, for the first time, out-of-order [out-of-order execution (OOE)] superscalar processors. To combat the state-space explosion associated with BMC, the proposed method starts by combining module-level abstraction-refinement with slicing to reduce the size of the model under verification. Next, an off-the-shelf BMC solver is used on the obtained extended finite-state machines to generate the leading sequences that are necessary to excite internal processor functions. Finally, constrained automatic test-pattern generation is used to cover all structural faults within every function excited by the obtained leading sequences. Experimental results show that the proposed method leads to extremely high fault coverage on the critical components corresponding to OOE operations in functional mode. The method therefore helps in tackling the over-testing problem that is inherent to the full-scan test approach.

Automation of Test Program Synthesis for Processor Post-silicon Validation

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-to-detect faults remain unidentified by these autogenerated test programs. Also, these approaches have considered fault models which have low correlation with the gate-level fault models. This paper presents a greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor. Subsequently, the overall coverage is also improved. A selection probability is estimated from the testability properties of the processor components and assigned to every instruction to accelerate the test synthesis. The range of performance and scalability are comprehensively evaluated on a configurable MIPS processor and a full-fledged 7-stage pipeline SPARC V8 Leon3 soft processor using behavioral fault models. The efficacy of our approach was explained by demonstrating the correlation between behavioral faults and gate-level faults of MIPS processor for the proposed scheme. Experimental results show that improved coverages of 96.32% for the MIPS processor and 95.8% for the Leon3 processor are achieved in comparison with the conventional methods, which have about 90% coverage on the average.

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

As technology scales, the increased vulnerability of modern systems due to unreliable components becomes a major problem in the era of multi-/many-core architectures. Recently, several on-line testing techniques have been proposed, aiming towards error detection of wear-out/aging-related defects that can appear during the lifetime of a system. In this work, firstly we investigate the relation between system test latency and test-time overhead in multi-/many-core systems with shared Last-Level Cache (LLC) for periodic Software-Based Self-Testing (SBST), under different test scheduling policies. Secondly, we propose a new methodology aiming to reduce the extra overhead related to testing that is incurred as the system scales up (i.e., the number of on-chip cores increases). The investigated scheduling policies primarily vary the number of cores concurrently under test in the overall system test session. Our extensive, workload-driven dynamic exploration reveals that there is an inverse relationship between the two test measures; as the number of cores concurrently under test increases, system test latency decreases, but at the cost of significantly increased test time, which sacrifices system availability for the actual workloads. Under given system test latency constraints, which dictate the recovery time in the event of error detection, our exploration framework identifies the scheduling policy under which the overall test-time overhead is minimized and, hence, system availability is maximized. For the evaluation of the proposed techniques, multi-/many-core systems consisting of 16 and 64 cores are explored in a full-system, execution-driven simulation framework running multi-threaded PARSEC workloads.

A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform

Software-based self-test (SBST) is an effective method to detect operational faults of a processor system. We propose an architectural approach to support high fault-coverage online SBST: Processor Shield, which tackles the difficult-to-test issues raised due to the protection of an operating system. The processor shield, including a software framework and design for testing hardware, creates an online self-testing environment without influencing other processes and on-bus devices even if the SBST fails. We present a case study that demonstrates SBST executions under Linux kernel on an ARMv5-compatible processor system. For CPU testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 93%. For cache control logic testing, the stuck-at fault coverage is over 99% while the transition fault coverage is higher than 95%. For RAM module testing, the fault coverage is nearly 100%. Cache SBSTs finish in a context-switch interval of less than 4 ms while CPU SBST finishes in less than 8 ms for 1-GHz clock. The hardware overhead of the processor shield is only 0.494% of the whole processor area. We also present an SBST-dynamic voltage and frequency scaling application that calibrates the dynamic minimal guardbands and helps achieving lower power consumption and mitigating transistor-aging effect.

New Techniques to Reduce the Execution Time of Functional Test Programs

The compaction of test programs for processor-based systems is of utmost practical importance: Software-Based Self-Test (SBST) is nowadays increasingly adopted, especially for in-field test of safety-critical applications, and both the size and the execution time of the test are critical parameters. However, while compacting the size of binary test sequences has been thoroughly studied over the years, the reduction of the execution time of test programs is still a rather unexplored area of research. This paper describes a family of algorithms able to automatically enhance an existing test program, reducing the time required to run it and, as a side effect, its size. The proposed solutions are based on instruction removal and restoration, which is shown to be computationally more efficient than instruction removal alone. Experimental results demonstrate the compaction capabilities, and allow analyzing computational costs and effectiveness of the different algorithms.

A Flexible Framework for the Automatic Generation of SBST Programs

Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.