Software-based Implementation Research Articles

Advanced Innovations in Electronic Control Units: Enhancing Performance and Reliability with AI

This paper proposes a methodology for the design of electronic control unit (ECU) hardware units with increased performance and reliability. Today's vehicles are equipped with dozens of ECUs that significantly influence the system's efficiency, reliability, performance, and safety. With the increased complexity of control algorithms and the environmental constraints that automotive systems operate, the robustness and efficiency of the ECUs are of utmost importance. In this work, an approach is proposed based on combining hardware redundancy, commercial field programmable gate arrays (FPGAs), and artificial intelligence strategies to provide increased redundancy checks and robust control. An additional redundancy is added to the hardware architecture of the ECU to include a parallel hardware unit. The two controlling units operate in parallel. The output of each of them is compared, allowing redundancy checks in the computation of the output variable (oV) of the system. The mathematical model of the ECU depicts the governing equations of the ECU in the form of differential equations, which results in a corresponding state-space configuration. These mathematical models are encoded into the field programmable gate array (FPGA) and processed in hardware, leading to an equivalent software-based implementation. To analyze the performance of both models within the ECU, an artificial neural network (ANN)-based strategy is proposed. The ANN depicts the governing equations of the ECU in the form of differential equations encoded in the form of sigmoidal functions. To analyze the reliability of the control action in the ECU, the temperature of the system is increased, which leads to a random variation of the system parameters. The variability of the ECU parameters leads to a deviation in the computation of the oV and the corresponding control action. The robustness of the control is determined in such conditions. A control law is determined to guarantee proper control action under variations in the governing equations of the system. This control law is represented by a simple algebraic equation, which can then be cast in various control strategies, such as look-up tables or fuzzy logic controllers. Several cases are simulated to assess the performance of the proposed control law for the hardware redundancy scheme, for the ANN-based equivalent software implementation approach, and for the additional fuzzy logic controller. The simulation results are analyzed concerning the requested oV and give insight into the performance and reliability of the proposed dedicated ECU design.

Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation

Computer-based machine learning algorithms that produce impressive performance results are computationally demanding and thus subject to high energy consumption during training and testing. Therefore, compact neuro-inspired devices are required to achieve efficiency in hardware resource consumption for the smooth implementation of neural network applications that require low energy and area. In this paper, learning characteristics and performances of the nanoscale titanium dioxide (TiO2) based synaptic device have been analyzed by implementing it in the hardware-based neural network for digit classification. Our model is experimentally validated by using 32-nm CMOS technology and the results demonstrate that the model provides high computational ability with better accuracy and efficiency in resource consumption with low energy and less area. The proposed model exhibits 20% energy gain and 16.82% accuracy improvement and 18% less total latency compared to the state-of-the-art Ag:Si synaptic device-based neural network. Furthermore, when compared to the software-based (i.e., computer-based) implementation of neural networks, our TiO2-based model not only achieved an impressive accuracy rate of 90.01% on the MNIST dataset but also did so with reduced energy consumption. Consequently, our model, characterized by a low hardware implementation cost, emerges as a promising neuro-inspired hardware solution for various neural network applications. The proposed model has further demonstrated outstanding performance in experiments involving both the MNIST and Fisher’s Iris datasets. On the latter dataset, the model exhibited notable precision (94.5%), recall (91.5%), and an impressive F1-score (92.9%), accompanied by a commendable accuracy rate of 93.04%.

Training an Ising machine with equilibrium propagation

Ising machines, which are hardware implementations of the Ising model of coupled spins, have been influential in the development of unsupervised learning algorithms at the origins of Artificial Intelligence (AI). However, their application to AI has been limited due to the complexities in matching supervised training methods with Ising machine physics, even though these methods are essential for achieving high accuracy. In this study, we demonstrate an efficient approach to train Ising machines in a supervised way through the Equilibrium Propagation algorithm, achieving comparable results to software-based implementations. We employ the quantum annealing procedure of the D-Wave Ising machine to train a fully-connected neural network on the MNIST dataset. Furthermore, we demonstrate that the machine’s connectivity supports convolution operations, enabling the training of a compact convolutional network with minimal spins per neuron. Our findings establish Ising machines as a promising trainable hardware platform for AI, with the potential to enhance machine learning applications.

VLSI Implementation of Chest X-Ray Image Segmentation Using Hybrid Clustering

Medical image segmentation plays a crucial role in various clinical applications, facilitating accurate diagnosis and treatment planning. In communication systems, particularly telemedicine and remote healthcare monitoring, real-time processing and transmission of medical images are essential for timely diagnosis and intervention. Leveraging VLSI technology for implementing Kmeans offers a promising solution to address the computational demands of image segmentation while meeting the stringent requirements of communication systems. Existing systems often rely on software-based implementations such as threshold segmentation, leading to significant computational overhead and latency, particularly in resource-constrained environments. Moreover, these implementations struggle to achieve real-time performance, hindering their practical utility in communication systems for healthcare. So, this work proposed VLSI-based approach aims to overcome these challenges by offloading the computational burden from the software to hardware, enabling parallel processing and efficient utilization of resources. By exploiting the inherent parallelism of the K-means algorithm and optimizing hardware architecture, our design ensures high throughput and low latency, making it suitable for real-time medical image segmentation in communication systems.

Urban sound classification using neural networks on embedded FPGAs

Sound classification using neural networks has recently produced very accurate results. A large number of different applications use this type of sound classifiers such as controlling and monitoring the type of activity in a city or identifying different types of animals in natural environments. While traditional acoustic processing applications have been developed on high-performance computing platforms equipped with expensive multi-channel audio interfaces, the Internet of Things (IoT) paradigm requires the use of more flexible and energy-efficient systems. Although software-based platforms exist for implementing general-purpose neural networks, they are not optimized for sound classification, wasting energy and computational resources. In this work, we have used FPGAs to develop an ad hoc system where only the hardware needed for our application is synthesized, resulting in faster and more energy-efficient circuits. The results show that our developments are accelerated by a factor of 35 compared to a software-based implementation on a Raspberry Pi.

Modeling Wind Turbines to Assess Impact of Offshore Wind Farms on Maritime X- and S-band Radars

This article discusses several aspects related to modeling the impact of offshore wind farms on maritime radar systems operating in the X and S bands. The first part of the paper focuses on theoretical models and analyses, taking into account radio shadowing and false radar echoes. Additionally, the issue of spatial modeling of wind turbines, with diffraction phenomena considered, is reviewed with the help of suitable propagation models. By relaying on a software-based implementation of the proposed model, the authors carried out a detailed simulation of the impact of wind turbines on radar systems operating in the X and S bands. The results of these simulations are presented and discussed in the second part of the article.

Enhancing functionality of two-rotor vibration machine by automatic control

The demand for the development of cyber-physical systems remains high across various production sectors. While some industries have made significant strides, others still require ongoing research and development efforts. This article delves into the application of feedback control for equipment in the processing industry, using a two-rotor vibration machine equipped with induction motors as a case study. Conventionally, such equipment is manually operated with the help of affordable constructive facilities, which does not align with the principles of Industry 4.0. In response, this paper explores an architecture for an automatic control system capable of handling various technological tasks, including mixing and transporting processed media. This architecture encompasses several components, such as real-time regulator tuning, control of the rotor speed loop, and/or adjustment of the phase shift between the rotors based on machine sensor measurements. A notable advantage of this control system lies in its complete software-based implementation. The article also presents the findings from full-scale experiments, demonstrating the capabilities and effectiveness of the proposed approach.

Design of exact reduct rough set hardware accelerator for early-stage diabetes risk prediction

Diabetes is a prevalent, chronic metabolic disorder worldwide. Detecting and predicting risks early are vital for timely intervention. In this paper, the design and implementation of an Exact Reduct Rough Set Hardware Accelerator is presented for early-stage diabetes risk prediction. The proposed hardware accelerator leverages the principles of Rough Set theory to identify essential features or attributes (reducts) from a large dataset that effectively predict the risk of diabetes at an early stage. The architecture of the hardware accelerator is optimized to efficiently handle large datasets commonly encountered in medical applications. It includes modules for data preprocessing, discernibility, matrix computation, and reduct determination. The proposed design is implemented on SPARTAN -6 Field Programmable Gate Array; it works on 100 MHz and supports 3 stages pipelining. The extensive experimentation, employing a comprehensive dataset of diabetes patients, unequivocally demonstrates the hardware accelerator's superior performance compared to traditional methods and software-based implementations. The Exact Reduct Rough Set Hardware Accelerator provides a powerful tool for medical professionals to identify patients at risk early on, enabling timely interventions and personalized care to improve patient health outcomes. The proposed accelerator contributes to the growing field of medical decision support systems and holds promise for broader applications in healthcare and beyond. The findings from this study can be seamlessly incorporated into the system-on-chip platform, contributing to the creation of intelligent tools for monitoring and managing diabetes. By offloading rough set computations to hardware accelerators on the wearable device, the data does not need to be continuously transmitted to external servers for analysis, ensuring user privacy and reducing communication overhead.

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.

CAMiSE: Content Addressable Memory-Integrated Searchable Encryption

Searchable symmetric encryption (SSE) is a special class of encryption schemes for computing directly over encrypted data. SSE aims to be significantly more efficient as compared to other solutions, such as fully homomorphic encryption (FHE), while leaking only minimal information to the adversary. SSE is particularly efficient and scalable for Boolean queries over large encrypted relational databases outsourced to third-party cloud service providers. However, practical implementations of SSE often suffer from performance bottlenecks due to randomised memory accesses for reads/writes and computation-intensive cryptographic operations. As a result, a gap exists today between theoretically efficient SSE algorithms and practically efficient SSE systems for real-world databases. In this paper, we address this longstanding open question that has otherwise hindered the widespread deployment of SSE over real cloud computing platforms. We propose –a fully associative memory-integrated framework for designing SSE systems with fast query processing over extremely large databases. We show a novel usage of custom-designed Content Addressable Memory (), together with robust data access policies, to bridge the memory wall in traditional SSE implementations by minimising storage-access latencies due to randomised look-up operations during searches. Coupled with dedicated hardware accelerators for cryptographic operations, achieves extremely fast and scalable query processing over encrypted relational databases. We prototype multiple well-known SSE algorithms and SSE data structures within our proposed framework. Our experiments show that these implementations achieve around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times$</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7\times$</tex-math> </inline-formula> speed-up over traditional software-based implementations while scaling smoothly to extensive real-world databases with millions of records.

An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks

Practical implementation of deep neural networks (DNNs) demands significant hardware resources, necessitating high computational power and memory bandwidth. While existing field-programmable gate array (FPGA)–based DNN accelerators are primarily optimized for fast single-task performance, cost, energy efficiency, and overall throughput are crucial considerations for their practical use in various applications. This article proposes a performance-centric pipeline Coordinate Rotation Digital Computer (CORDIC)–based MAC unit and implements a scalable CORDIC-based DNN architecture that is area- and power-efficient and has high throughput. The CORDIC-based neuron engine uses bit-rounding to maintain input-output precision and minimal hardware resource overhead. The results demonstrate the versatility of the proposed pipelined MAC, which operates at 460 MHz and allows for higher network throughput. A software-based implementation platform evaluates the proposed MAC operation’s accuracy for more extensive neural networks and complex datasets. The DNN accelerator with parameterized and modular layer-multiplexed architecture is designed. Empirical evaluation through Pareto analysis is used to improve the efficiency of DNN implementations by fixing the arithmetic precision and optimal pipeline stages. The proposed architecture utilizes layer-multiplexing, a technique that effectively reuses a single DNN layer to enhance efficiency while maintaining modularity and adaptability for integrating various network configurations. The proposed CORDIC MAC-based DNN architecture is scalable for any bit-precision network size, and the DNN accelerator is prototyped using the Xilinx Virtex-7 VC707 FPGA board, operating at 66 MHz. The proposed design does not use any Xilinx macros, making it easily adaptable for ASIC implementation. Compared with state-of-the-art designs, the proposed design reduces resource use by 45% and power consumption by 4× without sacrificing performance. The accelerator is validated using the MNIST dataset, achieving 95.06% accuracy, only 0.35% less than other cutting-edge implementations.

A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 μW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.

High-performance hard-input LDPC decoding on multi-core devices for optical space links

LDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multicore devices facilitate real-time implementations of digital communication systems, which were previously implemented into dedicated hardware devices. Previous works were done over the last decade on the implementation of Gbps decoders on programmable devices. However, these works focus on the soft input LDPC decoding algorithms. But, hard-input LDPC decoders are also required to design and prototype for instance next optical-based satellite communication systems. These systems should provide high throughput (≥10 Gbps) and low latency (≤1ms) internet links. In this article, the first software-based implementation of a hard-input multi-Gbps LDPC decoder is detailed. Thanks to different parallelization strategies and deeply optimized SIMD codes, throughput up to 7.5 Gbps is achieved when 10 Gallager-E iterations are executed onto an INTEL Xeon device making possible the design of software base station systems providing throughputs of tens of Gbps for optical system evaluation or base station design.

A Hand Gesture Recognition Circuit Utilizing an Analog Voting Classifier

Electromyography is a diagnostic medical procedure used to assess the state of a muscle and its related nerves. Electromyography signals are monitored to detect neuromuscular abnormalities and diseases but can also prove useful in decoding movement-related signals. This information is vital to controlling prosthetics in a more natural way. To this end, a novel analog integrated voting classifier is proposed as a hand gesture recognition system. The voting classifiers utilize 3 separate centroid-based classifiers, each one attached to a different electromyographic electrode and a voting circuit. The main building blocks of the architecture are bump and winner-take-all circuits. To confirm the proper operation of the proposed classifier, its post-layout classification results (91.2% accuracy) are compared to a software-based implementation (93.8% accuracy) of the same voting classifier. A TSMC 90 nm CMOS process in the Cadence IC Suite was used to design and simulate the following circuits and architectures.

FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search

Nearest neighbor (NN) search computations are at the core of many applications such as few-shot learning, classification, and hyperdimensional computing. As such, efficient hardware support for NN search is highly desired. In-memory computing using emerging devices offers attractive solutions for NN search. Solutions based on ternary content-addressable memories (TCAMs) offer high energy and latency improvements for NN search at the expense of accuracy. In this work, we propose a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. We evaluate the efficacy of FeFET MCAMs in the context of few-shot learning applications with different datasets. As an example, we achieve a 78.54% accuracy for a 5-way, 5-shot classification task for the mini-ImageNet dataset (only 1.5% lower than software-based implementations) when using a 3-bit MCAM for NN search. We consider the effects of FeFET threshold voltage variations on the application accuracy and analyze the area and search energy requirements of FeFET MCAMs for accurate operations. Our results indicate that MCAMs require 2× lower area and search energy than TCAMs to achieve the same accuracy. Furthermore, we experimentally demonstrate a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate the design concept.

A New Software-Based Optimization Technique for Embedded Latency Improvement of a Constrained MIMO MPC

Embedded controllers for multivariable processes have become a powerful tool in industrial implementations. Here, the Model Predictive Control offers higher performances than standard control methods. However, they face low computational resources, which reduces their processing capabilities. Based on pipelining concept, this paper presents a new embedded software-based implementation for a constrained Multi-Input-Multi-Output predictive control algorithm. The main goal of this work focuses on improving the timing performance and the resource usage of the control algorithm. Therefore, a profiling study of the baseline algorithm is developed, and the performance bottlenecks are identified. The functionality and effectiveness of the proposed implementation are validated in the NI myRIO 1900 platform using the simulation of a jet transport aircraft during cruise flight and a tape transport system. Numerical results for the study cases show that the latency and the processor usage are substantially reduced compared with the baseline algorithm, 4.6× and 3.17× respectively. Thus, efficient program execution is obtained which makes the proposed software-based implementation mainly suitable for embedded control systems.

High Accuracy Software-Based Clock Synchronization Over CAN

In distributed real-time communication systems, common knowledge of the global time is crucial. It prevents message violations on the bus and allows independent components to collaborate within a real-time system on a timely basis. Systems with hard real-time requirements need to have high precision and accuracy of time. This is achieved by hardware-supported frame time-stamping mechanisms as found in dedicated protocols, such as time-triggered CAN (TTCAN), Flexray, and time-sensitive networking (TSN)-enabled Ethernet. However, many microcontroller units are not specifically designed to provide such a hardware-based solution at the communication interface. Therefore, a software-based implementation of the time synchronization algorithm is needed. Nevertheless, some commercial off-the-shelf (COTS) microcontroller units already provide an IEEE 1588-enabled Ethernet interface, including a high-precision timer module with rate correction. This module can be used for time synchronization purposes to align a set of distributed clocks via various communication interfaces. This article investigates the accuracy of software-based and hardware-supported time synchronization algorithm over the controller area network (CAN) protocol using a COTS microcontroller. As a result, we present identified jitter and delay sources as well as the achieved time accuracy. We show that using an advanced timer module combined with additional system knowledge allows submicrosecond precision and accuracies.

Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse

Reuse-centric convolutional neural networks (CNN) acceleration speeds up CNN inference by reusing computations for similar neuron vectors in CNN’s input layer or activation maps. This new paradigm of optimizations is, however, largely limited by the overheads in neuron vector similarity detection, an important step in reuse-centric CNN. This article presents an in-depth exploration of architectural support for reuse-centric CNN. It addresses some major limitations of the state-of-the-art design and proposes a novel hardware accelerator that improves neuron vector similarity detection and reduces the energy consumption of reuse-centric CNN inference. The accelerator is implemented to support a wide variety of neural network settings with a banked memory subsystem. Design exploration is performed through RTL simulation and synthesis on an FPGA platform. When integrated into Eyeriss, the accelerator can potentially provide improvements up to 7.75\( \times \)in performance. Furthermore, it can reduce the energy used for similarity detection up to 95.46%, and it can accelerate the convolutional layer up to 3.63\( \times \)compared to the software-based implementation running on the CPU.

A review of optimisation and least-square problem methods on field programmable gate array-based orthogonal matching pursuit implementations

Orthogonal matching pursuit (OMP) is the most efficient algorithm used for the reconstruction of compressively sampled data signals in the implementation of compressive sensing. OMP operates in an iteration-based nature, which involves optimisation and least-square problem (LSP) as the main processes. However, optimisation and LSP processes comprise complex mathematical operations that are computationally demanding, and software-based implementations are slow, power-consuming, and unfit for real-time applications. To fill the research gap, we reviewed the optimisation and LSP techniques implemented on the FPGA platform as the hardware accelerator. Aspects that contributed to the performance, algorithm, and methods involved in the implemented works were discussed and compared. The methods were found to be improved when modified or combined. However, the best approach still depends on the requirement of the system to be developed, and this review is significant as a reference.

Implementation of hilbert transform based high-resolution phase unwrapping method for displacement retrieval using laser self mixing interferometry sensor

Laser self-mixing interferometry (SMI) is an attractive sensing scheme due to its compact, self-align, and cost-effective nature. In this work, an SMI based compute-intensive phase unwrapping method was implemented on FPGA. Before implementation, the algorithm was segmented into different processing stages. A limitation in PUM was also identified, and its signal processing-based solution was proposed. Lastly, the implementation of PUM was done on the targeted FPGA board. Results have shown 170 K times speed improvement compared to software-based implementation on a personal computer. Furthermore, the proposed implementation can process maximum target velocity up to 2.88 m/s. The proposed implementation consumes 0.7 W of dynamic power. From the results, the proposed implementation is suitable for low power and high bandwidth applications.