Soft Error Detector Research Articles

Coping with recall and precision of soft error detectors

Many methods are available to detect silent errors in high-performance computing (HPC) applications. Each method comes with a cost, a recall (fraction of all errors that are actually detected, i.e., false negatives), and a precision (fraction of true errors amongst all detected errors, i.e., false positives). The main contribution of this paper is to characterize the optimal computing pattern for an application: which detector(s) to use, how many detectors of each type to use, together with the length of the work segment that precedes each of them. We first prove that detectors with imperfect precisions offer limited usefulness. Then we focus on detectors with perfect precision, and we conduct a comprehensive complexity analysis of this optimization problem, showing NP-completeness and designing an FPTAS (Fully Polynomial-Time Approximation Scheme). On the practical side, we provide a greedy algorithm, whose performance is shown to be close to the optimal for a realistic set of evaluation scenarios. Extensive simulations illustrate the usefulness of detectors with false negatives, which are available at a lower cost than the guaranteed detectors.

Control Focused Soft Error Detection for Embedded Applications

Advances in integrated circuits present several key challenges in system reliability as soft errors are expected to increase with successive technology generations. Computing systems must be able to continue functioning in spite of these soft errors, necessitating the development of new methods for self-healing circuits that can detect and recover from these errors. We present an area-efficient control focused soft error detector (CNFSED) capable of nonintrusively detecting soft errors within the execution of a software application without modifications to the software application or the target processor. This soft error detector achieves an error detection rate greater than 90% for control errors and 85% of unmasked errors while incurring minimal area overhead.

Performance Analysis of a Memory ARQ Scheme with Soft Decision Detectors

An automatic repeat-request (ARQ) scheme with memory and soft error detectors has been recently proposed by Benelli. Its performance was studied mainly through computer simulation. In this paper, a generalized version of this ARQ scheme is examined. The selection of certain thresholds and weights to minimize the bit error rate in systems using a fixed number of packet repeats is considered. Finally, the evaluation of the average number of transmissions per packet in systems in which negatively acknowledged packets are retransmitted until successfully received is described.

An ARQ Scheme with Memory and Soft Error Detectors

This paper describes a technique for increasing the efficiency of an ARQ communication system utilizing error detection codes. In this technique the blocks containing errors are not discarded at the receiver, as in the conventional ARQ systems. Such blocks are retained in order to make use of the information contained in them. A reliability value is associated to each demodulated symbol; this reliability value is updated every time a new retransmission is made, even if the vector received is in error. The process of updating the symbols often eliminates automatically the errors introduced by the channel. The results obtained by means of a simulation show that this method offers a considerable reduction in the average number of retransmissions, in comparison with conventional ARQ systems.