SoC Environment Research Articles

A United Architecture For AES/Present Ciphers and Its Usage in a Soc Environment

Abstract: In order to monitor the operating status of vehicles, it is necessary to collect vehicle operating data in real time through IoT devices and analyze these data. However, the collected data has the characteristics of multi-source heterogeneous, network resources are limited and server performance is poor. It is difficult to truly realize data processing in real time. In addition, data needs to be transmitted over the network, it is particularly important to ensure the safety of data transmission. Considering the above problems, it is necessary to structure the data and define a unified data format to facilitate data transmission and analysis. At the same time, improve the server communication program and improve the server's concurrent processing capabilities. In addition, considering that data needs to be transmitted over the network, in order to ensure that the data is not stolen or tampered with, the PRESENT lightweight encryption algorithm is adopted to ensure the safety of data transmission. Compared with encryption algorithms such as AES, this algorithm has much lower hardware requirements. This article combines the characteristics of the project and uses the number of communications between the device and the server to achieve the dynamic key update which is approximately one-time pad, and greatly improves the security of the data.

Design, integration and implementation of crypto cores in an SoC environment

PurposeThe paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Low Power Bidirectional Voltage Level Translator using Power Gating

now a day’s, the demand for SoC based systems increasing. In SoC environment, multiple supply voltages are required because various subsystems of the system operate with different supply voltages. The communication between these systems is difficult and increases power consumption. The solution to this problem is to use a Voltage level translator/shifter between them. In this paper, a low power voltage level translator using power gating is proposed. By using this translator bidirectional voltage translator is implemented. In bidirectional voltage level translator, the data is translation between core logic and pad drivers and vice versa is possible with reduced power consumption and delay. In this paper, the power consumption reduces from 104uw to 6.25 pw at Vdd 1.8V. Delay is reduced from 19ns to 0.2 ns.

IJARCCE - Computer and Communication Engineering

The increasing popularity of Cloud Computing as an attractive alternative to classic information processing systems has increased the importance of its correct and continuous operation even in the presence of faulty components. But fault tolerance is still a crucial issue in SOC. By utilizing VM technology, the performance and fault isolation of cloud resources can be provisioned on demand in a fine grained, multiplexed manner. The design of the DOPS resource allocation method, utilizes the proportional share model. The key idea is to redistribute available resources among running tasks dynamically, where these tasks could use up the maximum capacity of each resource in node. To locate for qualified nodes in the SOC environment, a fully decentralized range query protocol called PG CAN has been tailored for DOPS. Pointer Gossiping is responsible for making sure every node in the system eventually knows important information about every other node’s state including those that are unreachable. The sensitivity analysis conducted on the model, violates certain assumptions that creates more impact on the dynamic optimal resource allocation of multiple attributes due to faulty components. Hence an analysis will be made in a VM environment, aiming to find a node already present in the network and identify a zone that can be split. Thereby, updating the routing tables of nodes neighbouring the newly split zone. During this step, faulty nodes will be identified and re-routing will be done either by merging zones or managing with the neighbour node, all performed dynamically by the SOC system.

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs

Contention in performance-critical shared resources affects performance and quality-of-service (QoS) significantly. While this issue has been studied recently in CMP architectures, the same problem exists in SoC architectures where the challenge is even more severe due to the contention of shared resources between programmable cores and fixed-function IP blocks. In the SoC environment, efficient resource sharing and a guarantee of a certain level of QoS are highly desirable. Researchers have proposed different techniques to support QoS, but most existing works focus on only one individual resource. Coordinated management of multiple QoS-aware shared resources remains an open problem. In this paper, we propose a class-of-service based QoS architecture (CoQoS), which can jointly manage three performance-critical resources (cache, NoC, and memory) in a NoC-based SoC platform. We evaluate the interaction between the QoS-aware allocation of shared resources in a trace-driven platform simulator consisting of detailed NoC and cache/memory models. Our simulations show that the class-of-service based approach provides a low-cost flexible solution for SoCs. We show that assigning the same class-of-service to multiple resources is not as effective as tuning the class-of-service of each resource while observing the joint interactions. This demonstrates the importance of overall QoS support and the coordination of QoS-aware shared resources.

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration

A highly multi-channel on-chip signal monitor and off-chip waveform acquisition processor established analog circuit diagnosis against environmental disturbances in SoC. An array of 53 distributed probes followed by a single shared waveform acquisition kernel is embedded in a 0.18-μm CMOS experimental on-chip test bench. In combination with the off-chip processor materialized in FPGA and a host PC, fully automated on-chip waveform monitoring achieves high-throughput data acquisition of 300ms per sample point with adaptive 10-bit timing and voltage resolutions at a minimum LSB of 100ps and 400μV, respectively. Analog signals of interest in a 1.5-bit conversion stage of a pipeline ADC were evaluated in terms of their response to substrate noises that globally existed in a chip. On-chip diagnosis derives in-depth findings relating to dynamic, large-signal, and sensitive behaviors of analog circuits in a real SoC environment, far beyond simulations with inevitably limited capacity.

Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.

Transaction policies for service-oriented computing

Service-oriented computing is emerging as a distributed computing model where autonomous services interact with each other using standard Internet technology. In addition to the application-specific functions that services provide (different) services may also support (different) sets of protocols and formats addressing extra-functional concerns such as transaction processing and reliable messaging. This raises the need for services to complement their functional service descriptions with descriptions of extra-functional capabilities, requirements, and/or preferences, which must be matched and enforced for service interactions. In this paper, we address the problem of transactional coordination in service-oriented computing. We argue for the use of declarative policy assertions to advertise and match support for different transaction styles (direct transaction processing, queued transaction processing, and compensation-based transaction processing), and introduce the concept of and system support for transaction coupling modes as the policy-based contracts guiding transactional business process execution. We focus on concrete, protocol-specific policies that apply to relevant Web services specifications. Using transaction policies and our middleware system, we are able to support a reliable SOC environment.