Smaller Critical Path Research Articles

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.

Comparative Performance Analysis of High Speed Low Power Area Efficient FIR Adaptive Filter

This paper presents the comparative performance of an adaptive FIR filter for a Delayed LMS algorithm. The delayed error signal was used to obtain a Delayed LMS algorithm to allow efficient pipelining for achieving a small critical path and area efficient implementation. This paper presents hardware efficient results (device utilization parameters) and power consumed. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for a low voltage perspective are shown. The synthesis results showed that the artix-7 CMOS family achieves the lowest power consumption of 1.118 mW with 83.18 % device utilization. Different Precision strategies, such as the speed optimization and power optimization, were imposed to achieve these results. The algorithm was implemented using MATLAB (2013b) and synthesized on the Leonardo spectrum.

A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial Basis

This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%.

A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial Basis

This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%.

A Word-Level Finite Field Multiplier Using Normal Basis

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-level finite field multiplier using normal basis is proposed. The proposed architecture takes d clock cycles to compute the product bits, where the value for d, 1 ≤ d ≤ m, can be arbitrarily selected by the designer to set the tradeoff between area and speed. When there exists an optimal normal basis, it is shown that the proposed design has a smaller critical path delay than other word-level normal basis multipliers found in the literature, while its circuit complexities are moderate and comparable to the others. Different word size multipliers were implemented in hardware, and implementation results are also presented.

Re-scheduling invocations of services for RPC grids

RPC-based grid infrastructures emphasize on the composition of services on a large number of computing resources. The key issue to reach high performance is to enable exploitation of parallelism on services invocations and communications. Moreover, this process should be transparent to reuse legacy codes. In this paper we present H OMA, an IDL compiler and a run-time support for automatic detection of the parallelism of invocations and their data dependencies on a set of CORBA objects. On homogeneous architecture, H OMA is accompanied by a predictable cost model. In the case of an application with a small critical path, among p processors the speed up of H OMA versus CORBA is asymptotically O ( p ) . The illustrations on a case study in computational chemistry validate our cost model.

Parametric minimum hardware QR-factoriser architecture for V-BLAST detection

The authors introduce a new architecture for the core processor for a V-BLAST detector. This architecture uses only two low complexity CORDIC processors for QR factorisation. The parameterised feature of the controller and address generator blocks provides a scalable architecture for the implementation of QR factorisation for a square matrix of any dimension. The reduced hardware complexity of the processors and its simple parameterised controller are two outstanding features of the architecture, resulting in a more suitable alternative architecture for QR factorisation than triangular systolic arrays. A comprehensive analysis of parameters influencing the hardware implementation and their effects on the error performance of the V-BLAST detector has been presented. The implementation of the proposed architecture on an Altera Stratix FPGA device results in a very small critical path delay. This provides a platform for the fast matrix triangularisation for applications requiring high data rates such as MIMO V-BLAST detectors. The maximum throughput values of up to 367 Mbit/s are reachable using this novel QR-factorisation architecture for the V-BLAST detector.