Small Transistors Research Articles

Analysis of Channel Current Noise in Small Nanoscale Metal Oxide Semiconductor Field Effect Transistors.

The shrinkage of metal oxide semiconductor field effect transistor (MOSFET) to the small size of the nanoscale results in changes in their channel current noise composition. This paper determines the channel current noise composition of 90nm MOSFET through experiments, and according to the device material and noise characteristics analysis, the channel current noise of 90nm and below is obtained, which not only contains thermal noise and suppressed channel shot noise, but also adds suppressed gate tunneling shot noise and cross-correlation noise. Then, Monte Carlo simulation of 10nm MOSFET noise is further used to determine the channel current composition of small size nanoscale devices. Subsequently, based on the device structure and fundamental characteristics of channel current noise, the channel current noise model is established. Finally, this model is employed to analyze the relationship between thermal noise, suppressed shot noise, cross-correlation noise, and channel current noise in relation to bias parameters and device characteristics. The theoretical results are basically consistent with the experimental and the simulated results, and the channel noise increases with the increase of bias voltage. This achievement holds promise for enhancing the operational efficiency, reliability, and lifetime of nanoscale small-sized MOSFET devices.

Small Feature-Size Transistors Based on Low-Dimensional Materials: From Structure Design to Nanofabrication Techniques.

For several decades after Moore's Law is proposed, there is a continuous effort to reduce the feature-size of transistors. However, as the size of transistors continues to decrease, numerous challenges and obstacles including severe short channel effects (SCEs) are emerging. Recently, low-dimensional materials have provided new opportunities for constructing small feature-size transistors due to their superior electrical properties compared to silicon. Here, state-of-the-art low-dimensional materials-based transistors with small feature-sizes are reviewed. Different from other works that mainly focus on material characteristics of a specific device structure, the discussed topics are utilizing device structure design including vertical structure and nano-gate structure, and nanofabrication techniques to achieve small feature-sizes of transistors. A comprehensive summary of these small feature-size transistors is presented by illustrating their operation mechanism, relevant fabrication processes, and corresponding performance parameters. Besides, the role of small feature-size transistors based on low-dimensional materials in further reducing the small footprint is also clarified and their cutting-edge applications are highlighted. Finally, a comparison and analysis between state-of-art transistors is made, as well as a glimpse into the future research trajectory of low dimensional materials-based small feature-size transistors is briefly outlined.

From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects

With the swift progression of semiconductor technology, the transition from Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to Fin Field-Effect Transistors (FinFETs) and further to Gate-All-Around Field-Effect Transistors (GAAFETs) presents significant potential for the future of electronic devices and systems. This article delves into the intricate applications, challenges, and prospective evolutions associated with FinFET and GAAFET technologies. Findings suggest that these technologies are particularly apt for low-power logic systems, high-performance computing, and artificial intelligence domains. However, as dimensions shrink, challenges pertaining to heat dissipation, leakage, and manufacturing consistency become prominent. Despite these hurdles, the horizon for semiconductor technology remains bright, encompassing exploration of alternative materials such as Germanium and 2D compositions and innovative designs like U-shaped Field-Effect Transistors and Complementary Field-Effect Transistors. As the industry continues its relentless pursuit of even more efficient, smaller transistors, the exploration of alternative materials and diversification in architecture may play a pivotal role in future developments. In essence, while the semiconductor sphere confronts challenges, relentless innovation promises a future brimming with even more efficient and compact transistor technologies.

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

Thionated stereoisomer enhance the mixed conduction, ambient stability and mechanical deformability for high-performance small molecular n-type organic electrochemical transistors

High performance stretchable organic mixed ionic-electronic conductors with highly stability are extremely demanding for flexible bioelectronics. However, very little is known about the correlation between the mixed conduction and both stability and mechanical deformability of n-type small molecular organic electrochemical transistors (OECTs). Herein, a stereoisomerism was reported as an effective platform to address these challenges by introducing a concept of coupling rigid tetrachloro perylene diimides (PDI) skeleton and amorphous thionation stereoisomer to afford the stereoisomerism of dithionated oligo(ethylene glycol) functionalized PDI (2S-gPDI). In further, for the first time we carried out proof-of-concept experiments to build the correlations between both chemical/microstructures and the thin/thick films’ ambient stability as well as mechanical deformability based on this novel small-molecule mixed conductors. Our results reveal that the thionation stereoisomerism render 2S-gPDI higher figure of merit μC* and ambient stability as well as higher mechanical deformability owing to the lower LUMO levels, porous film morphology and lower degree of film crystallinity, when compared with the parent unthionated gPDI-based mixed conductors. It is envisioned that the coupling rigid skeleton and amorphous stereoisomer concept will guide the next generation of high stable small-molecules stretchable OECTs.

HPC Hardware Design Reliability Benchmarking With HDFIT

Chips pack ever more, ever smaller transistors. Fault rates increase in turn and become more concerning, particularly at the scale of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">High-Performance Computing</i> (HPC) systems: on one hand, hardware fault protection is costly - more than 10% silicon area for floating-point units; on the other, HPC users expect correct application output after the anticipated time of computation, but workloads are seldom bit-reproducible and tolerances in output are allowed for. Benign hardware faults causing errors within these tolerances are therefore acceptable: however, with abstract reliability targets such as ’undetected failures per time,’ current HPC system design does not allow for pursuing trade-offs between reliability and performance with respect to faults. To address the above, we propose a user-centric reliability benchmark to specify HPC system reliability targets, allowing for better performance optimizations in hardware design, while meeting HPC user expectations. Our open-source <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hardware Design Fault Injection Toolkit</i> ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HDFIT</i> ) enables - for the first time - end-to-end hardware design reliability experiments: from netlist-level fault injection to application output error. In a proof of concept we present an HPC <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">general matrix multiply</i> (GEMM) reliability study, targeting a series of popular applications, and using HDFIT to benchmark an open-source GEMM accelerator.

Aqueous-alcohol-processable indolo[3,2-b]indole-based crystalline small molecules for organic field effect transistors with oligo(ethylene glycol) side chains

We address an eco-friendly aqueous process approach to obtain efficient/stable small molecule organic field effect transistors (OFETs). Penta-ethylene glycol (PEG) side chains were introduced at N-positions of the rigid backbone structures of indolo[3,2-b]indole(IDID), thus enabling the formation of PEG-IDIDF. The PEG-IDIDF exhibited remarkable solubility in alcohol (ethanol) solvent. The X-ray diffraction and grazing incidence wide angle X-ray scattering measurements indicate that the suitable addition of a typical cosolvent, water, to ethanol solvent significantly contributes to an enhancement in film crystallinity and molecular stacking orientation features than those of the PEG-IDIDF film processed by using a single solvent. Consequently, the PEG-IDIDF OFETs processed by the ethanol water cosolvent (90:10) ratio yielded the enhanced hole mobility of 4.07 × 10−3 cm2 V−1 s−1 and current on/off ratio of 106, which was one of the highest reliable mobility for small molecules OFETs processed with an alcohol solvent.

Taking Moore's Law to New Heights: When transistors can't get any smaller, the only direction is up

Perhaps the Most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we've been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Characterization of Single-Event Upsets Induced by High-LET Heavy Ions in 16-nm Bulk FinFET SRAMs

For advanced technology nodes, the static random-access memories (SRAMs) are highly vulnerable to the single-event upsets (SEUs), especially the multiple cell upsets (MCUs), by a high energy ion strike, which is due to the small transistor size and close proximity of the sensitive regions. However, the narrow connection between the fin and the bulk region for FinFET inhibits the charge collection compared to the planar transistor structure. In this work, heavy ion tests were conducted for 16 nm bulk FinFET dual-port SRAM at two high linear energy transfers (LETs) of 60 MeV∙cm2/mg and 85 MeV∙cm2/mg. The non-saturating behavior of the SEU cross-sections and event cross-sections for a bit cell is observed even over the LET of 60 MeV∙cm2/mg due to the expanding of the sensitive area surrounding the array and the cutting-off area in the FinFET SRAM cells. The distribution curves of the MCU event probabilities for different MCU cluster sizes show the Single-bit upset (SBU) occupies the largest probability of all the single-event cluster sizes, which exhibits the inhibition capability of the Fin structure against the upsets induced by high energy particles. The parasitic bipolar effect is also serious for 16nm FinFET SRAM as former planar SRAM, but the charge sharing effect is effectively inhibited due to the narrow connection between the fin and the bulk region for FinFET. Results presented in this paper will help designers estimate the Error Correcting Code (ECC) and interleaving design parameters for radiation hardened SRAM designs at the 16 nm FinFET process.

Effects of molding temperature on delamination of small outline transistor (SOT)

Delamination of small outline transistor (SOT) package has been a challenge to ensure good package reliability. Molding process parameter optimization is a practical & cost-effective alternative to reduce delamination of the plastic package. First, selective molding parameters, namely, molding temperature, transfer speed, transfer pressure & pre-heat temperature was varied in a full factorial experiment to determine the significance of each factor. It is observed from the complete factorial analysis that molding temperature was the most significant factor concerning delamination. Next, one factor at a time (OFAT) experimental design was conducted to confirm moulding temperature’s repeatability. Molding temperature was identified as a significant factor on determining the delamination response of SOT packages. Lowering mold temperature resulting to lower percentage of delamination however proven to have an adverse on package curing density.

Detection of pH and Urea with an Extended Gate Field-Effect Transistor Based Microsensor

Here, extended gate field-effect transistor-based (EGFET) microsensors have been developed for high sensitive detection of pH and urea. EGFET was made by integrating with a microelectrode. Briefly, the EGFET-based pH microsensor was developed by modifying the surface of a microelectrode with polypyrrole (PPy) via electropolymerization and integrating it with a small, simple and inexpensive metal oxide semiconductor field-effect transistor (MOSFET). As for the EGFET-based urea microsensor, urease enzyme was immobilized in PPy. The measurements of pH and urea were made in solutions at different pH values and urea concentrations, respectively. The results showed that the pH microsensor had a very good sensitivity of 67 mV/pH in a pH range of 5-12. Similarly, the EGFET-based urea microsensor showed a linear response range of 10-9 to 10-5 M urea with sensitivities of 35.5 mV/decade urea and 10 µA/decade urea. The reported EGFET-based pH and urea microsensors have great potential for use in the biomedical field, especially in applications where local analysis is required.

Navigating the Seismic Shift of Post-Moore Computer Systems Design

Reports on the history and development of computer aided design systems. In quick succession between 1964 and 1971, our field saw the proposal of Moore’s law,1 the coining of the term “computer architecture,”2 and the introduction of the first microprocessor.3 For much of the five decades since then, we have benefitted extraordinarily from both the dynamism of Moore’s law transistor scaling and the stable durability of the hardware–software abstractions of computer architecture. The dynamic duo of Moore’s law and computer architecture have allowed massive scaling to occur, and also to be navigated smoothly with relatively little software impact. For example, in the late 1980s and early 1990s, surges in power density occurred as we reached challenging limits in very large scale integration (VLSI) designs based on bipolar transistors; a technology transition from bipolar to complementary metal–oxide–semiconductor (CMOS) occurred with relatively little impact or awareness from the software portion of the computing community.4 Over the past 10–15 years however, more fundamental shifts have occurred. For example, Dennard scaling,5 a companion phenomenon to Moore’s law stating that power density could remain stable while transistor sizes shrank, is reaching physical limits. This means that further Moore’s law increases in transistor counts are becoming more complex and are only achieved with great effort and at higher power-density costs. Furthermore, as we reach fundamental physical limits in the functioning of small semiconductor transistors, Moore’s law itself is being challenged by the increased physical effort and financial expense required to maintain transistor scaling trends.

Investigation on characteristics of millisecond solid-phase crystallized silicon films annealed by atmospheric pressure DC arc discharge micro-thermal-plasma-jet and their application to bottom-gate thin film transistors fabrication

Millisecond solid phase crystallization (SPC) of silicon film induced by micro-thermal-plasma-jet is a potential method for small grain bottom-gate thin-film transistors (TFTs). The characteristics of millisecond SPC films under the conditions of scanning speed (v) from 500 to 900 mm s−1 were investigated. The films show good crystalline quality when formed at a slow v. The crystallinity estimated by micro-Raman spectroscopy is 61% when v was 500 mm s−1. Hall effect measurement results indicate that under v at 500 mm s−1, the resistivity is 1.36 × 10−3 Ωcm, the carrier concentration is 3.41 × 1020 cm−3, and the carrier mobility is 12.2 cm2 Vs−1. Millisecond SPC films surface reduce larger than 76% roughness compared to that of the melted film surface. Bottom-gate TFTs fabricated with millisecond SPC film, which annealed under conditions close to melted condition, show high field effect mobility of 28 cm2 Vs−1 and good uniformity.

Tin Whisker Formation on Small Outline Transistors Assembled Using Bismuth-Containing Lead-Free Solder Alloys After Long-Term Ambient Temperature, High Humidity Storage Part 3: In-Depth Characterization and Mechanisms

With the introduction of environmental legislation such as the Restriction of Hazardous Substances (RoHS), lead (Pb)-free materials have made their way into the electronics manufacturing industry. One issue that has emerged is that Pb-free solder alloys can initiate and grow tin whiskers under specific conditions. These whiskers are thin, highly conductive filaments which have the potential to grow and can cause field failures in many applications. Most concerning with respect to tin whiskering are high reliability applications such as aerospace, automotive, and medical.&#x0D; Bismuth (Bi) is being considered for inclusion in solder alloys to replace the current industry standard (SAC 305) and provide improved thermomechanical and vibration reliability. In this paper, we discuss whisker formation of several Bi-bearing alloys after long-term (12,000 hours), ambient high humidity (25°C/85% RH) storage. Three alloys containing Bi, in addition to SAC 305 (Sn-3.0Ag-0.5Cu), were considered. These alloys were Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and Senju (Sn-2.0Ag-0.7Cu-3.0Bi). The boards were fabricated with electroless nickel immersion gold (ENIG) and immersion tin (ImmSn) finishes and populated with parts having Cu and Fe42Ni alloy leads and chip parts, with half of assemblies cleaned and half cleaned and contaminated with low levels of NaCl.&#x0D; This paper is the third in a series of three in which we share more in-depth characterization of features of interest from the small outline transistor (SOT) inspection. Discussion regarding the role of Bi in the overall stress state of the joint will also be provided.

A 24–28-GHz Doherty Power Amplifier With 4-W Output Power and 32% PAE at 6-dB OPBO in 150-nm GaN Technology

A 24-28-GHz two-stage GaN Doherty power amplifier (PA) is designed and characterized. At millimeter-wave (mm-wave) frequencies, the low output impedance of the auxiliary transistor loads the Doherty combining network, which lowers the power added efficiency (PAE) in back-off. In this design, a small periphery auxiliary transistor is used to increase the output impedance of the auxiliary transistor. The periphery ratio of the auxiliary and the main transistors is 77%. Even though, compared to symmetric Doherty PAs, the load modulation of the main transistor is reduced, this amplifier still achieves 32% and 23% PAE at 6 and 9-dB output power back-off, respectively. Attributing to the small auxiliary transistor, the amplifier obtains a small signal gain of 19 dB. The maximum output power of the amplifier is 4 W with a peak PAE of 42%.

Energy Storage and Reuse in Negative Capacitance

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu \text{m}$ </tex-math></inline-formula> , in an inverter circuit. At 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors.

Ask me anything: Michelle Simmons

Michelle Simmons is director of the Centre of Excellence for Quantum Computation and Communication Technology at the University of New South Wales, Australia. A pioneer in atomic-scale silicon devices, she has built the world’s smallest transistor, the narrowest conducting wires, 3D atomic electronics and the first two-qubit silicon gate. In 2018 Simmons was named Australian of the Year.

Tin Whisker Growth on Electronic Assemblies Soldered with Bi-Containing, Pb-Free Alloys

With the introduction of environmental legislation, lead (Pb)-free materials have made their way into the electronics supply chain. As a result, tin whiskers may initiate and grow under specific conditions. Sufficiently long whiskers may cause in-field short circuit failures, which are a serious concern in many high-reliability applications such as aerospace, automotive, and medical. There are efforts in developing third generation Pb-free solder alloys to replace tin-silver-copper (Sn-Ag-Cu, or SAC). Bismuth (Bi) has been considered for inclusion in SAC alloys to reduce melting point and improve reliability. In this study, we examine whisker formation on small outline transistor (SOT) components assembled with SAC-Bi alloys after ambient temperature (25°C) or high temperature (85°C), high humidity (85% RH) storage. Four alloys were considered—Senju M42 (Sn-2.0Ag-0.7Cu-3.0Bi), Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and SAC305 (Sn-3.0Ag-0.5Cu). The assemblies were finished with immersion tin (ImmSn) or electroless nickel immersion gold (ENIG), and some were intentionally contaminated prior to exposure. It was found that SAC305 tended to grow longer whiskers than SAC-Bi alloys, though more whiskers were found on the latter. Particle Stimulated Nucleation (PSN) of recrystallization of the β-Sn matrix, influenced by Bi precipitation, appears to influence dynamic recrystallization (DRX), the mechanism for whisker growth.

Characteristics and Applications of CAAC-IGZO FET with Gate Length of 13nm

A field-effect transistor (FET) with a gate length of 13 nm having a c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) channel was fabricated. The CAAC-IGZO FET has an off-state leakage current of 200 yA/μm, a cutoff frequency of 60GHz, and a maximum oscillation frequency of 16GHz. A CAAC-IGZO FET, though it is a small transistor, withstands voltages up to approximately 2.5 V. It also has stable current characteristics with less temperature dependence than Si devices. We have constructed an equivalent-circuit model of the CAAC-IGZO FET and designed an RF amplifier to show CAAC-IGZO FET's applicability to the GHz-range RF circuitry.

Tin Whisker Formation on Small Outline Transistors Assembled Using Bismuth-Containing Lead-Free Solder Alloys After Long-Term Ambient Temperature, High Humidity Storage Part 2: Statistical Analysis

With the introduction of environmental legislation such as the Restriction of Hazardous Substances (RoHS), lead (Pb)-free materials have made their way into the electronics manufacturing industry. One issue that has emerged is that Pb-free solder alloys can initiate and grow tin whiskers under specific conditions. These whiskers are thin, highly conductive filaments which have the potential to grow and can cause field failures in many applications. Most concerning with respect to tin whiskering are high reliability applications such as aerospace, automotive, and medical.&#x0D; Bismuth (Bi) is being considered for inclusion in solder alloys to replace the current industry standard (SAC 305) and provide improved thermomechanical and vibration reliability. In this paper, we discuss whisker formation of several Bi-bearing alloys after long-term (12,000 hours), ambient high humidity (25°C/85% RH) storage. Three alloys containing Bi, in addition to SAC 305 (Sn-3.0Ag-0.5Cu), were considered. These alloys were Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and Senju (Sn-2.0Ag-0.7Cu-3.0Bi). The boards were fabricated with electroless nickel immersion gold (ENIG) and immersion tin (ImmSn) finishes and populated with parts having Cu and Fe42Ni alloy leads and chip parts, with half of assemblies cleaned and half cleaned and contaminated with low levels of NaCl.&#x0D; This paper is the second in a series of three in which we share quantitative statistical analysis from the whisker inspection of the small outline transistor (SOT) components. It was found that on ImmSn surface finishes, the longest whiskers were found on SAC, however the longest whiskers were found on Bi-bearing alloys for ENIG. In addition, whiskers were found to generally grow in regions where the tin coverage is thin, and, on ENIG-finished assemblies, near the PCB, likely due to galvanic corrosion between the solder and the finish chemistry.