Smaller Layout Size Research Articles

5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity

A high-voltage-tolerant buck converter with a novel adaptive power transistor driver is proposed in this paper. In order to minimize the RON of the cascode power transistor, the proposed scheme uses optimized and separated driving voltages for bias of the pMOS and nMOS power transistors. This increases not only the conversion efficiency, but also the maximum allowable load current for the transistor driver with small layout size, when compared to the buck converter with the earlier scheme. The measurements show that when the supply voltage is 2.5 V and the load current is 150 mA, the efficiency of the buck converter with the earlier scheme is 82%, whereas the efficiency of the buck converter with the proposed scheme is 92%, showing a maximum improvement of 10%. The designed buck converter uses the 0.35- μm-thick gate oxide CMOS process, and at 2.5-5 V of voltage, can supply up to 380 mA of load current. The total chip size is 2.7 mm2.

Fusion of technology in analysis, design and comparison of numerical techniques for rectangular Microstrip patch antenna

In today's scenario higher integration and smaller layout size are the two major trends in RF and Microwave industry, lead to more prominent role in electromagnetic high order effects. Recent years...

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB

EM Methods for MIC Modeling and Design: An Overview

Higher integration and smaller layout size, two major trends in today’s RF/microwave industry, lead to more prominent electromagnetic high order effects. In this paper, the authors present a survey of existing electromagnetic techniques to compute such effects in microwave integrated circuits, highlighting their specific advantages/disadvantages for a circuit designer.

ANALYSIS OF THE MIXED COUPLING IN BILATERAL MICROWAVE CIRCUITS INCLUDING ANISOTROPY FOR MICs AND MMICs APPLICATIONS

Higher integration and smaller layout size, two major trends in today’s industry, lead to more prominent electromagnetic coupling with direct applications in the RF/microwave area such as directional couplers, filters, multiplexers, shifters, delay lines, etc. In the present work, an efficient hybrid-mode method is presented for a rigorous characterization of the coupling in multilayer bilateral microwave circuits including anisotropy effects. Various types of planar configurations were considered including microstrip, finline and coplanar structures, but the proposed approach can easily be extended to any form of coupled lines. To fully characterize bilateral multilayer circuits in millimetre wave region with an arbitrary number of conductors, closed forms of dyadic Green’s functions were determined in the spectral domain, with use of the Galerkin technique. The computed results show good agreement with data available in the literature. Furthermore, two original configurations based on three line bilateral couplers were computed and validated using neural network models.