Small Chip Area Research Articles

Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator

In this paper, a fully integrated memristive Chua’s chaotic circuit based on the voltage-controlled oscillator is proposed. The memristor replaces the nonlinear diode, and the VCO (voltage-controlled oscillator) replaces the LC oscillator, eliminating the need for diodes, resistors, capacitors, and other complex circuit structures. The proposed chaotic circuit occupies a small chip area, only 0.0045 mm2, and achieves low power consumption of 2.8267 mW. The chaotic circuit is fabricated using the SMIC 180 nm CMOS process. The simulation results demonstrate that the VCO circuit can generate a frequency output ranging from 358 MHz to 1.1 GHz by varying Vc from 0 V to 2.8 V, with a power supply of 3.3 V. The value range of the Lyapunov index is 1.015 ∼1.03. The circuit offers advantages such as a stable power supply, low power consumption, and a small chip area.

Novel high-voltage GaN CAVET with high threshold voltage and low reverse conduction loss

A novel GaN current-aperture vertical electron transistor (CAVET) with an energy band pinning (EBP) structure (EBP-CAVET) is proposed and investigated by simulations. The EBP-CAVET is featured with hybrid contacts on the p-GaN layer, locally having Ohmic contact combined with Schottky gate metals in the longitudinal direction. The Ohmic contact is shorted to the source electrode and the Schottky gate metals are shorted to the gate electrode. The conduction band (Ec) in the gate region is modulated by the alternately arranged contacts. In the Ohmic contact region, Ec remains a fixed value, which acts as an energy band pinning and suppresses the variation of the Ec in the gate region. In the on-state (VGS > 0 V) and blocking-state with high VDS, the EBP structure inhibits the Ec shifting downwards in the gate region to achieve a high threshold voltage (Vth), a low leakage current density (Jdss), and a high breakdown voltage (BV). In the reverse conduction state (VDS < 0 V &VGS ≤ 0 V), the EBP structure suppresses the Ec shifting upwards to achieve a low and independent of gate bias reverse turn-on voltage (VRT). The proposed EBP-CAVET achieves a high Vth of 2.10 V, a VRT of 0.69 V, a low Jdss of 3.1 × 10−11 A/cm2 at VDS = 1000 V, a high BV of 1660 V. Compared with an integrated Schottky barrier diode or fin diode in a field effect transistor (FET), the EBP structure occupies a much smaller chip area. Thus, the EBP-CAVET achieves a low specific ON-resistance (Ron,sp) of 1.19 mΩ cm2 and an extremely high power-figure-of-merit (PFOM) up to 2.32 GW/cm2. Consequently, the proposed structure presents a new design concept and enhances the application potential for GaN CAVET with high Vth and low reverse conduction loss.

Area Efficient and Linear MMIC Based Ka Band Power Amplifier for 5G Communication Systems

This work presents a monolithic microwave integrated circuit (MMIC) based power amplifier (PA) with single 150 nm GaN high electron mobility transistor (HEMT) using broadband matching. For the proposed amplifier, two stage L-type biasing network is designed. In order to provide good linearity, low Q, broader bandwidth and optimized chip area, band pass filter (BPF) type matching network is proposed. The topology and parameter selection is done by performing proper load pull analysis. This helps in achieving wide band matching to maintain low Q factor. Thus the proposed amplifier is evaluated with post layout EM simulation data. For the 26 GHz band of 5G communication, proposed amplifier has a small signal gain of 11 dB for 21-27.4 GHz. The amplifier offers 33.42 dBm saturated output power and good linearity. The designed PA provides 31.35 dBm output power, 26% power added efficiency (PAE) and 29% drain efficiency (DE) at 1 dB compression with IP3 of 39.67 dBm for 26 GHz band. The designed PA has less complexity and small chip area of 4.3 mm2.

A 20.65-to-40.55 GHz Dual-Core Quad-Mode VCO With Mode-Independent Transformer-Switching Technique in 65-nm CMOS

This paper proposes a dual-core quad-mode millimeter-wave (mm-wave) voltage-controlled oscillator (VCO) using a compact multi-mode LC network with a modeindependent switched transformer technique. On top of the dualmode main LC tank, the mode-independent switched transformer technique introduces two additional oscillation modes, further extending the frequency tuning range with a small chip area overhead, while the mode-independent feature reduces the cost of switch off-capacitance compared with the conventional switched transformers. Implemented in 65nm CMOS process, the proposed VCO achieves a measured octave frequency tuning range from 20.65 to 40.55 GHz. The measured best phase noise is -131.04 dBc/Hz at 10 MHz offset from 20.65 GHz. The measured best figure-of-merit (FoM) is 187.25 dBc/Hz at 10 MHz offset from 26.66 GHz, corresponding to a figure-of-merit of tuning range and area (FoMTA) of 216.72 dBc/Hz thanks to the proposed compact multi-mode LC network and the mode-independent switched transformer technique. The VCO consumes 9.75-to-18.85 mW from a 0.65 V supply voltage. The core area is 0.048 mm2.

Performance Analysis of a Reconfigurable Mixer Using Particle Swarm Optimization

In this article, a novel 1.8-5 GHz downconversion mixer is presented. The mixer is designed and simulated using SiGe 8HP 130 nm CMOS process technology. The proposed mixer is implemented by incorporating a double-balanced configuration, active inductor, and current mirror techniques. For performance optimization of the proposed mixer, different algorithms such as the genetic algorithm (GA), inclined plane system optimization (IPO) algorithm, and particle swarm optimization (PSO) algorithm have been used. Compared to existing works, this design shows an enhanced conversion gain (CG), a third-order input intercept point (IIP3), and return loss ( S 11 ) at the expense of the noise figure (NF). Additionally, the design consumes low power and covers a small chip area compared to other state-of-the-art devices. PSO shows the most promising results when compared to other optimization algorithms’ results. According to the measurement results after PSO optimization, the mixer attains a maximum CG of 25 dB, an IIP3 of 4 dBm, and a NF of 5.2 dB at 5 GHz, while consuming only 15 mW of DC power. The mixer operates at 1.2 V and covers 0.8 mm2 die area.

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

An 18–19.2 GHz Voltage-Controlled Oscillator with a Compact Varactor-Only Capacitor Array

This paper presents a K-band CMOS cross-coupled pair voltage-controlled oscillator (VCO) that utilizes the varactor-only capacitor network. The proposed circuit features low parasitics and a compact capacitor network, such that the varactor in the analog tuning path directly affects the oscillation frequency with a large gain of the VCO, and the varactor in the digital tuning path results in minimal noise sources, thus achieving low phase noise for the automotive FMCW radar application. This VCO was designed using TSMC 65 nm technology, and the post-layout simulation results show a stable oscillation across 18–19.2 GHz, a minimum phase noise of −105.9 and −128 dBc/Hz at 1- and 10-MHz offset frequencies while dissipating 21 mW of power from a 1 V supply. Furthermore, no notable variations in phase noise are observed across the oscillation frequency tuning range. It reveals a figure of merit (FOM) of −178.3 dBc/Hz while using a varactor-only capacitor array and occupying a small chip area.

A novel hardware implemented programmable controller adapted to cooperate with AI tuning algorithms in real time systems

A novel, transistor level PID (proportional–integrating–derivative) controller is proposed that may be easily coupled with various AI algorithms responsible for adjusting its main factors. In our work we focus on a discrete-time digital approach, as it facilities realization a flexible and programmable structure that can be quickly re-configured depending on varying environment conditions. One of the novelties of the proposed solution is its parallel and asynchronous structure that requires only simple 2-phases clock. Each of the P, I and D blocks is realized as a separate channel with its own multi-bit multiplier, a summing circuit and a short delay line (in case of I and D blocks). The circuit features small chip area. For the input signals, and the coefficients of the controller being encoded as 8-bit signals the number of transistors does not exceed 13,000, which translates into the chip area not exceeding 0.1 mm2 in the CMOS 130 nm technology. Data rate of the controller can achieve 200–330 MSamples/s, with power dissipation not exceeding 1 mW. The proposed solution is suitable for miniaturized microsystems, for example high performance MEMS devices, in which small sizes and high data rate become very important features.

A Single-Inductor–Triple-Output Buck DC-DC Converter With Electromagnetic Gated Low Dropouts for Higher Resistance to Electromagnetic and Power Side-Channel Attacks With 3B Minimum Traces to Disclosure Improvement in Internet of Things Applications

The security protection of IoT urges the design of low electromagnetic interference (EMI) and small power signature in power chips. To achieve high security, small chip area, and high efficiency, this paper proposes a single-inductor triple-output (SITO) buck DC-DC converter with Electromagnetic (EM) gated Low Dropouts (LDO) to reduce the EM leaked signature. Experimental results shows that the peak value of electromagnetic interference noise can be reduced from 88.44dBlV to 54.92dBlV, complying with EN 55032 Class B specifications. In addition, it can achieve 3 billion (B) minimum traces to disclosure (MTD) under power side-channel attack, which is at least three times improvement compared to prior-arts.

New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~67\%$ </tex-math></inline-formula> improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1154.69~\mu \text{m}^{2}$ </tex-math></inline-formula> and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.

FPSNET: An Architecture for Neural-Network-Based Feature Point Extraction for SLAM

The hardware architecture of a deep-neural-network-based feature point extraction method is proposed for the simultaneous localization and mapping (SLAM) in robotic applications, which is named the Feature Point based SLAM Network (FPSNET). Some key techniques are deployed to improve the hardware and power efficiency. The data path is devised to reduce overall off-chip memory accesses. The intermediate data and partial sums resulting in the convolution process are stored in available on-chip memories, and optimized hardware is employed to compute the one-point activation function. Meanwhile, address generation units are used to avoid data overlapping in memories. The proposed FPSNET has been designed in 65 nm CMOS technology with a core area of 8.3 mm2. This work reduces the memory overhead by 50% compared to traditional data storage for activation and overall by 35% for on-chip memories. The synthesis and simulation results show that it achieved a 2.0× higher performance compared with the previous design while achieving a power efficiency of 1.0 TOPS/W, which is 2.4× better than previous work. Compared to other ASIC designs with close peak throughput and power efficiency performance, the presented FPSNET has the smallest chip area (at least 42.4% reduction).

A 28V NMOS power switch and bootstrap driver with integrated PA gate driver

For low power dissipation and area reasons, achieving a small size driver circuit for high power amplifiers (HPAs) is critical. Performing high-voltage driving and control technology based on NMOS power transistor is very important to achieve high efficiency. This paper proposes a fully integrated NMOS transistor driving circuit with an integrated on-chip NMOS power LDMOS transistor, and a CMOS gate driver for the HPA is also integrated capable of handling 1 μF capacitor and dozens of mA loads. This strategy ensures that the drain supply of HPA is modulated and gate power supply is supported simultaneously. The bootstrap driver circuit proposed in this work is suitable for continuous wave applications, and has faster response speed and smaller chip area. Measurements from a test chip in 180 nm high voltage BCD technology confirm the proposed strategy achieved in this paper.

Design of DC–DC Buck Converter Based on Improved Voltage-Mode COT Control

In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13[Formula: see text][Formula: see text]m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5[Formula: see text]V and the output voltage is 3.3[Formula: see text]V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value.

A fully integrated chaos generator based on voltage controlled oscillator

A new integrated chaos generator based on Voltage-Controlled-Oscillators (VCO) is proposed in this paper. The proposed generator consists of a nonlinear resistor and RC coupling circuit integrated with VCO. It is fully integrated instead of using discrete components compared with the traditional chaotic circuits. The proposed circuit exhibits excellent performances in the stable power supply, low power consumption, and small chip area cost. This chaotic circuit is fabricated in SMIC 180 nm CMOS process and it occupies a chip area of 0.039 mm2. The simulation results show that the proposed circuit could work in the frequency range from 11 MHz to 36 MHz with the maximum 2.0892 mW power consumption with a 1.8 V power supply. The range of the Lyapunov exponent is from 0.5628 to 2.2136. It shows potential application values of the designed fully integrated chaotic circuit.

A Compact 112-Gbaud PAM-4 Silicon Photonics Transceiver for Short-Reach Interconnects

For next generation highly integrated transceivers, silicon photonics (SiP) has attracted widespread interest in using mature CMOS production processes to manufacture high-yield, low-cost photonic integrated circuits (PIC) with the potential for integration with CMOS electronics. SiP now routinely integrate GeSi electroabsorption modulators (EAM) and GeSi waveguide photodiodes which have high responsivity and possess 3-dB electro-optic bandwidth of over 65 GHz. Their ultra-compact dimensions make it possible for multi-channel transceivers to be realized on a small chip area. In this paper, we demonstrate the high-speed capability of these devices incorporated with optimized digital signal processing (DSP) for 100 Gbaud+ PAM-4 signaling. Using integrated GeSi-EAM and GeSi-photodiode fabricated at a commercial foundry, we carried out intensity modulation and direct detection (IM-DD) transmission experiments in C-band using PAM-4, for both back-to-back and SSMF transmission at 1 km and 1.5 km. Under a 6-dB system bandwidth of ∼43GHz we attained, with the help of DSP equalization, a record 112 Gbaud (224 Gb/s), 108 Gbaud (216 Gb/s) and 100 Gbaud (200 Gb/s) are achieved over back-to-back, 1 km and 1.5 km SSMF transmission respectively, with a bit-error-rate (BER) below the hard-decision forward-error-correction (HD-FEC) threshold of 3.8E-3.

Electrode-free photonic electric field sensor on thin film lithium niobate with high sensitivity.

A high-sensitivity electrode-free photonic electric field (E-field) sensor is introduced on a thin film lithium niobate (TFLN) platform. An integrated Michelson interferometer, constructed by low-loss etched lithium niobite (LN) waveguide structures, is implemented as the sensing element. The sensing arms are designed in a spiral shape, which facilities a long interaction length with the external E-field in a small chip area. A minimal detectable E-field amplitude of 8.43 mV/m/Hz1/2 is experimentally obtained. The metal-electrode-free design of the proposed device avoids affecting the E-field to be measured and enables a vectorial response with a measured extinction ratio (ER) of 38 dB.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

A compact Ka‐band limiter‐low noise amplifier MMIC with high power capability

AbstractThis paper presents a 30–36 GHz limiter low‐noise amplifier (limiter‐LNA) MMIC for high power and high mobility millimeter‐wave radar systems. The PIN‐diode limiter network and the LNA are codesigned to realize high input‐power handling capability, good small‐signal performance, and small chip area. A two‐state matching capacitor is presented to improve both the input‐power handling capability at the high input‐power level and the input return loss at the small‐signal level. The proposed circuit is fabricated with a combined PIN/0.15‐µm‐GaAs‐pHEMT process. The limiter‐LNA is capable of handling 39 dBm continuous wave (CW) input‐power without failure with only two limiter stages. The measured noise figure is 1.8–2.5 dB, the small‐signal gain is 18.5 ± 0.5 dB, the output power at 1 dB compression point is larger than 11 dBm, and the dc power consumption is 72 mW. The chip area, including testing pads, is only 2.1 mm × 1.0 mm. This limiter‐LNA MMIC is believed to have the highest input‐power handling capability and smallest chip area among limiter‐LNA MMICs at this frequency range reported up to date.