Sliding DFT Research Articles

Improved Sliding DFT Filter With Fractional and Integer Frequency Bin-Index

Improved Sliding DFT Filter With Fractional and Integer Frequency Bin-Index

A Digital Interfacing Circuit Based on Sliding DFT Bins for Capacitive Sensors

A digital interfacing circuit (DIC) based on sliding discrete Fourier transform (SDFT) bins has been proposed for lossy capacitive sensors. The proposed interfacing circuit consisting of an analog sensing circuit and an analog-to-digital converter (ADC)-field-programmable gate array (FPGA)-based DIC. The sliding DFT bin-1 is employed as a quadrature signal generator to obtain in-phase and quadrature signals of the input supply voltage provided to the analog sensing circuit. The output sinusoidal signal of analog sensing circuit is correlated with the in-phase and quadrature signals separately and then averaged with SDFT bin-0 for computing sensing capacitance and resistance values. The proposed method is implemented in FPGA and tested for capacitance measurement range of 11 pF–5.27 nF with the maximum relative percentage error of 1.36%. The nonlinearity error is < 0.37% FS and FSS. Moreover, the suitability of the proposed interface for humidity measurement has been explored and validated experimentally with saturated salt solutions. Furthermore, the interdigitated capacitance is fabricated and tested with the proposed digital interface for the capacitance range of 30–122 pF, which finds an application in capacitive touchpad.

On the Low Complexity Implementation of the DFT-Based BFSK Demodulator for Ultra-Narrowband Communications

The DFT-based demodulator for BFSK has been introduced for applications where the received signal experiences a carrier frequency offset (CFO) much larger than the symbol rate. The Ultra-Narrowband (UNB) communication techniques have been introduced for implementing the emerging Low Power Wide Area Networks (LPWAN). Since UNB communication is prone to CFO, a DFT-based BFSK demodulator is an interesting option for this type of communication. However, for proper operation in a large frequency offset, the DFT-based demodulator requires a complex window synchronization which is not desirable for low power nodes. The main source of complexity, is calculating the DFT of a window which slides over the preamble. In this work, the complexity is alleviated by considering the window synchronization algorithm and its implementation together. First, a new window synchronization algorithm is proposed which is designed such that an efficient class of implementations of the sliding DFT (SDFT), called Single Bin SDFT (SB-SDFT) in this work, can be used. Moreover, a new stable implementation of SB-SDFT is designed to enable zero-padding which is required by the demodulator. The complexity of the proposed algorithm implemented using the SB-SDFT, scales more efficiently compared to the conventional algorithm when the range of tolerable CFO increases. Using the proposed method, for a CFO tolerance in the order of 14.5 times the symbol rate (±14.5 kHz for a symbol rate equal to 100 Hz), the number of complex operations is reduced by more than 85% (and memory by 90%) compared to the conventional method.

A Non-Feedback-Loop and Low-Computation- Complexity Algorithm Design for a Novel 2-D Sliding DFT Computation

This paper presents a forward-path, novel, two-dimensional (2-D) sliding discrete Fourier transform (SDFT) algorithm based on the column-row 2-D DFT concept and the shifted window property. After applying a descending dimension method (DDM), a mixed-radix and butterfly-based structure can be further employed to effectively implement the proposed algorithm. Conceptually, it has many advantages, including greater stability, more accuracy, and less computational complexity because there are no extra feedback loops in the calculation. The evaluation results are based on the following conditions: (1) the window size (N) to 16 × 16; (2) the test pattern is an SVC grayscale video, and the formats are CIF and 4CIF with 30fps; (3) one multiplication involves four real multiplications and two real additions. The proposed 2-D SDFT method clearly reduced the number of multiplications by 43.8% and only increased the number of additions by 33%, compared with the state-of-the-art Park's method. Additionally, for the first 100 frames of the CIF and 4CIF sequences, the proposed method saves 10.8% and 10.9% of the processing time, respectively, on average. Overall, the proposed DDM-based 2-D SDFT algorithm can be applied to calculate not only 1-D but also 2-D SDFT spectrum, and are especially appropriate for hybrid applications.

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed design is scalable with the transform length and the calculable number of the DFT bins, and can provide high throughput for a single bin evaluation. The paper also presents the comparison of the conventional and the modulated SDFT architectures based on CORDIC algorithm in terms of the angle-approximation and the truncation errors. The proposed design is synthesized on the Xilinx Virtex-6 FPGA platform and is implemented in ASIC using 90 nm standard cell library.

A High Resolution Method for Acoustic Localization in Far-field Based on Sliding DFT Algorithm

In order to accurate the time delay estimation and orientation localization, in this paper, we are aimed at finding a high resolution algorithm to improve the deviation in the far-field source localization. Compared with the traditional method based on the cross-correlation algorithm which often corresponds with the interpolation algorithm, the method of Sliding DFT is a novel time delay estimation approach based on the Sliding DFT analysis window, which is more comprehensive and accurate. The signal is specified into a singularity frequency signal and this algorithm of Sliding DFT uses the sample number at the maximum magnitude of the spectrum as the first estimation and utilize its corresponding phase offset for compensation with the aim to estimate the time delay of the signal, which is a rather new method applied to the acoustic localization field in this paper. The simulation includes a simple acoustic source with singularity frequency using the traditional cross-correlation algorithm and the improved Sliding DFT algorithm, accompanied with the matrix transformation method to compute the position of the assumed signal. After calculating and comparing the statistic of both algorithms, the improvement of the accuracy can be easily seen.

Controller Adjustment Method by Frequency-Domain Fictitious Reference Iterative Tuning Using Sliding DFT

Controller Adjustment Method by Frequency-Domain Fictitious Reference Iterative Tuning Using Sliding DFT

Online Identification of a Mechanical System in Frequency Domain Using Sliding DFT

A proper real-time system identification method is of great importance in order to acquire an analytical model that sufficiently represents the characteristics of the monitored system. While the use of different time-domain online identification techniques has been widely recognized as a powerful approach to system diagnostics, the frequency-domain identification techniques have primarily been considered for offline commissioning purposes. This paper addresses issues in the online frequency-domain identification of a mechanical system with varying dynamics; particular attention is paid to detect the changes in the system dynamics. A closed-loop online identification method is presented that is based on a sliding discrete Fourier transform at a selected set of frequencies. The method is experimentally validated by a closed-loop controlled servomechanism with a limited stroke and time-varying parameters.

A Power-Line Interference Canceler Based on Sliding DFT Phase Locking Scheme for ECG Signals

A power-line interference (PLI) removal method is proposed based on a previously published sliding discrete Fourier transform (SDFT) phase locking scheme (PLL), which extracts the nonstationary sinusoids from the electrocardiogram (ECG) signal. The proposed PLI canceler consists of SDFT PLL as a vital element, which can track the variation in center frequency of the PLI either 50 or 60 Hz. The PLI canceler involves the adaptive sampling frequency control in which the sampling frequency of SDFT filter is adaptively adjusted according to the center frequency variation of the interference. Since the in-phase and quadrature components of SDFT filter can provide instantaneous sinusoidal and cosinusoidal interference signals, the SDFT PLL is capable of tracking amplitude, phase, and frequency of the interference. Additional resonators of different bin indices are augmented with SDFT PLL to handle the dominant odd harmonics of PLI. Furthermore, the SDFT PLL is cascaded with another SDFT bin to eliminate the baseline wander present in the real-time ECG signal. The adaptive PLI canceler based on SDFT PLL offers the tracking capability of variant PLI, attenuation of 40 dB, less acquisition time of 0.2 s for a variant PLI of ±5 Hz, removal of dominant odd harmonics, and baseline wander with expense of sampling frequency. Experimental results prove the efficacy of the proposed method in nonstationary sinusoidal interference extraction. Experimental investigation on SDFT PLL using field programmable gate array demonstrates the feasibility of digital implementation of the proposed algorithm.

A Frequency Demodulation Technique Based on Sliding DFT Phase Locking Scheme for Large Variation FM Signals

A new frequency demodulation scheme based on sliding discrete Fourier transform (SDFT) and a phase locking scheme (PLL) is proposed for extracting message signal from sinusoidal frequency modulated signals. A wide operating range of the PLL, especially the pull-in range is utilized in extracting modulation signal from the large deviation FM signals. As fundamental frequency SDFT bin is involved in the design, the SDFT PLL scheme is suitable for demodulating linear FM signals of frequency range between d.c. and second harmonic of the carrier. Simulation and experimental results prove the fast acquisition behavior and competence of the SDFT PLL in modulation signal retrieval.

A speech enhancement method using the sliding DFT

In this paper, we propose a novel noise reduction of speech signals using sliding DFT (SDFT) which is based on the spectral subtraction method. The spectral subtraction method reduces noise by subtracting the spectrum of noise estimated from an input signal and is a relatively simple and effective technique. We use SDFT to obtain the frequency spectra of speech signals. As is well known, to obtain the successive N-points output, SDFT requires only N times of complex multiplication, although the Fast Fourier Transform (FFT) requires Nlog2N times that. Thus SDFT is computationally simple as compared with FFT. The frame length, N, is determined based on the pitch period. In this paper, the pitch period is estimated by using an ideal low-pass filter and the analytic signal that is obtained from speech signals by the Hilbert converter. Finally, it is shown that the proposed method has good performance for speech enhancement.