Skew Compensation Research Articles

Theoretical and Practical Bounds on the Initial Value of Clock Skew Compensation Algorithm Immune to Floating-Point Precision Loss for Resource-Constrained Wireless Sensor Nodes

ABSTRACT We revisit our prior work on clock skew compensation immune to floating-point precision loss and provide practical as well as theoretical bounds on the initial value of the skew-compensated clock based on a systematic analysis of the errors of floating-point operations; by practical bounds, we mean the actual values of the theoretical bounds calculated at resource-constrained computing platforms like WSN nodes equipped with 32-bit single-precision floating-point format. Numerical examples demonstrate that the proposed practical bounds on single-precision floating-point format do not violate the theoretical bounds and thereby can guarantee the correctness of the clock skew compensation on resource-constrained computing platforms.

Anti-Singularity Clock Recovery and Rx/Tx IQ Skew Compensation Scheme

Anti-Singularity Clock Recovery and Rx/Tx IQ Skew Compensation Scheme

A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

Receiver IQ Imbalance and Skew Compensation for High Order Modulation Formats by Frequency Domain 4 × 2 MIMO

A typical coherent front-end may encounter imperfections, such as amplitude imbalance, phase imbalance and skew, between four sampling channels. These receiver (Rx) imperfections, together with traditional chromatic dispersion (CD) compensation, would induce in-phase (I) and quadrature (Q) mixing, which greatly degrades the system performance. In this work, we propose a modulation format independent frequency domain (FD) 4 × 2 multi-inputs and multi-outputs (MIMO) based on decision directed least mean square (DD-LMS) algorithm to solve this problem. Compared with traditional 2 × 2 MIMO, it enables to compensate for all of Rx imperfections. Compared with 4 × 4 MIMO, it can eliminate performance penalty induced by the IQ mixing after optical fiber transmission. Compared with traditional time domain 4 × 2 MIMO, the proposed FD 4 × 2 MIMO has advantages in terms of complexity and parallel processing. We also evaluate the Rx imperfections compensation capability, noise tolerance tolerance, polarization tracking capability, residual CD and transmitter imperfections tolerance of the proposed equalizers. The proposed FD 4 × 2 MIMO algorithms are verified by numerical simulation with different modulation formats and experimentally validated with 40 Gbaud polarization division multiplexed 16-ary quadrature amplitude modulation signal.

Clock Skew Compensation Algorithm Immune to Floating-Point Precision Loss

We propose a novel clock skew compensation algorithm based on Bresenham's line drawing algorithm. The proposed algorithm can avoid the effect of limited floating-point precision (e.g., 32-bit single precision) on clock skew compensation and thereby provide high-precision time synchronization even with resource-constrained sensor nodes in wireless sensor networks.

An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications

The timing skew between signals reduces the timing margin of the receiver and limits the data rate of the parallel link. This issue becomes more critical for applications with many IO pins, such as a high bandwidth memory (HBM). The inter-signal skew compensation scheme for many IO pins requires not only de-skew performance but also the minimization of area and power overheads. In this brief, we propose an inter-pin skew compensation scheme using bypass-controlled all digital delay locked loops (ADDLL). The adoption of the proposed bypass control register that operates with a binary search algorithm, such as the successive approximation register (SAR), allows the digital control delay line (DCDL) controller to be embedded in the delay line. This can alleviate the limitation of bandwidth, which is a disadvantage of SAR and occupies smaller area than SAR whereas maintaining the fast lock time. The circuit is fabricated using a 28 nm CMOS technology with a 1 V supply voltage and an area of 0.0009 mm2 for one de-skew module. The measured result shows that inter-signal skew is reduced to less than 3 ps for 2 Gb/s/pin $\times8$ parallel signals.

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation

Skews between data and strobe signals can occur in HBM transceivers due to process and voltage variations across the base die. Skew compensation is introduced into the deserializers of our quarter-rate single-ended receiver for next-generation unmatched source-synchronous HBM interfaces. Data and strobe signals are energy-efficiently realigned by using a 45° strobe phase DQS45. This phase, which is equidistant between quadrature strobe phases DQS0 and DQS90, is generated by a digital type phase interpolator of our receiver. The transceiver, including the proposed receiver, was designed and fabricated in a 65nm CMOS process. The receiver corrects skews to within 7.8ps at a data-rate of 6.4Gb/s, with an energy cost of 0.83pJ/bit per pin.

A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation

A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation

Widely Linear Equalization for IQ Imbalance and Skew Compensation in Optical Coherent Receivers

In this paper, an alternative approach to design linear equalization algorithms for optical coherent receivers is introduced. Using widely linear (WL) complex analysis, a general analytical model it is shown, where In-phase/quadrature (IQ) imbalances and IQ skew at the coherent receiver front-end are naturally included in channel equalization problem. Next, the problem of chromatic dispersion (CD) compensation after imbalanced and skewed coherent detection is analyzed. Based on the analytical models obtained it is demonstrated that, under the presence of such receiver front-end imperfections, the complexity of the channel equalization filter which is able to provide optimal performance, on the minimum mean square error sense, will scale proportionally to twice the complexity of CD compensation, if standard zero-forcing equalization of CD is applied as first equalization procedure. For the last, it is shown that, by applying the WL complex analysis, one can derive a complex-valued adaptive equalizer structure which is able to compensate for linear IQ-mixing effects at the receiver front-end. By extensive numerical simulations, the performance versus complexity of the proposed equalizer is shown to match the predictions of the analytical models derived.

High-Rate Skew Estimation for Tape Systems

Abstract: In several recent magnetic tape drive designs, an actuator with two degrees of freedom has been adopted for joint skew- and track-following control. This enables the removal of flanges from guide rollers in the tape path, thus avoiding debris build-up, tape-edge damage, and high-frequency lateral tape motion. Skew compensation is needed to keep the head perpendicular to the direction of tape motion to enable read-while-write functionality in the presence of large lateral tape excursions originating from the removal of roller flanges. In this paper, we present a novel skew estimator that generates skew estimates at a high rate for an extended range of allowable tape-to-head skew values. A skew estimate is given by the sum of a fractional and an integer part, extracted from information provided by two parallel synchronous servo channels operating on timing-based servo patterns. The fractional part is obtained from the accurate measure of timing intervals between dibit correlation peaks, whereas the integer part is derived from longitudinal position information. The new method was implemented in an FPGA and verified experimentally using a commercial tape drive.

Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit

A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz.

Blind Receiver Skew Compensation and Estimation for Long-Haul Non-Dispersion Managed Systems Using Adaptive Equalizer

Imbalances between the four sampling channels of a coherent detector with polarization diversity can rapidly degrade system performance. One of these imbalances, namely the receiver skew, becomes increasingly important when higher symbol rates, higher modulation orders, and low roll-off pulse shapes are used. Here, we evaluate the performance of receiver skew compensation based on a complex-valued multiple-input multiple-output 4 × 2 adaptive equalizer that is tolerant to large residual chromatic dispersion. In addition, we derive skew estimation from converged equalizer taps. Both the adaptive equalizer and the derived estimator are validated experimentally with offline processing through long-haul transmission of 46 Gbaud signal over a non-dispersion-managed test bed. The transmitted signal is Nyquist pulse shaped with a root-raised-cosine filter with 0.1 roll-off factor, polarization division multiplexed, and modulated with 16-ary quadrature amplitude modulation.

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip

Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips since most mainstream memories use a source-synchronous interface. This paper presents a new Skew Measurement and Compensation Module (SMCM) design for off-chip skew calibration from Time Domain Reflectometry (TDR) measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution. Circuit complexity is reduced through use of the proposed automatic edge detection method which controls coarse/fine operations. We also present skew compensation circuits which can de-skew off-chip signals based on the skew calibration. The SMCM occupies a small area, making it suitable for implementation in a Built-Off Test (BOT) chip. The circuits were implemented using a 130 nm technology in a Built-Off Test Interface (BOTI) developed for 800 Mbps DDR2 memory functional test.

Skew compensation in energy recovery clock distribution networks

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.